Patent
Method and apparatus for generating phase locked digital clock signals
TLDR
In this article, a method and apparatus for generating two phase-locked digital clocks of different word rates was presented for a graphic and alphanumeric computer display terminal, where the master and slave clock generators were used to generate output pulses at every N-th and M-th clocks of a common clock.Abstract:
@ A method and apparatus for generating two phase locked digital clocks of different word rates particularly suited for a graphic and alphanumeric computer display terminal. Master and slave clock generators are used to generate output pulses at every N-th and M-th clocks of a common clock. A phase lock loop including the master clock generator and a phase lock counter dividing the common clock by the factor of the least common multiple of N and M is used to synchronize the slave clock generator.read more
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Patent
Method and apparatus for phase-locking a plurality of display devices and multi-level driver for use therewith
TL;DR: In this article, a method and apparatus for phase-locking a plurality of display devices and multi-level driver for use therewith is presented, where each of the display devices displays an image under the control of a distinct clock having distinct clock rate.
Patent
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TL;DR: In this paper, a slave clock generation system and a method suitable for use with synchronous telecommunications networks was proposed, where a multiplexer (20) selects a reference clock from a number of available sources (12), each of which can be at its own spot frequency, based on a predetermined selection order.
Patent
Method and system for synchronizing multiple subsystems using one voltage-controlled oscillator
Erik Hogl,Ulrich Fiedler +1 more
TL;DR: In this paper, a method for synchronizing multiple subsystems using one voltage-controlled oscillator was proposed, which includes transmitting a phase and frequency aligned output of a voltage controller oscillator to each subsystem within a digital system.
Patent
Synchronous clock frequency conversion circuit
Mansur Robert P,Imtiaz I Piracha +1 more
TL;DR: In this paper, a conversion system that provides compatibility between the internal system bus architecture of one computer and an external bus that operates on a different frequency includes a clock logic circuit for generating a clock signal that is synchronized with the internal clock for the computer system.
Patent
Method and system for reduced metastability between devices which communicate and operate at different clock frequencies
TL;DR: In this article, a method and system for improved communication between devices is presented for the detection of metastability due to the difference between the first clock rate and the second clock rate.
References
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Patent
Programmable multiple frequency ratio synchronous clock signal generator circuit and method
TL;DR: In this article, a circuit and method for providing two or more synchronous clock signals whose respective frequency ratios can be readily changed with respect to a master clock signal frequency is presented.
Patent
Clock synchronization signal generating circuit
TL;DR: In this article, the scale variable counter is selectively set to (n-1)-, n- or (n+1)-scale mode responsive to the control signal from the control circuit to generate an output signal which is clock-synchronized with the input clock signal.
Patent
Procede et dispositif de synchronisation d'une frequence de commande avec une frequence etalon et leur application a la chronometrie
TL;DR: Synchronisation par blocage en phase Pour obtenir une frequence appropriee, p ex 786 432 Hz (= 3 x 2**18) a partir d'une frequence etalon, P ex celle de 77 500 Hz (= 31 x 5 *4 *4 x 2 *2 *2) d'un radioemetteur, on multiplie cette derniere par les facteurs premiers qui lui manquent, puis on la divise par ceux qu'elle renferme en trop Ici on multipl