Showing papers on "Master clock published in 1993"

Distributed time synchronization system and method

Abstract: A distributed time synchronization system and method synchronizes nodes within a frequency hopping spread spectrum (FHSS) local area network (LAN) group to a virtual master clock value. Each node system of the present invention comprises a CPU, an input device, a display device, a printer or hard copy device, a given amount of RAM and ROM memory, a data storage device, a local clock, a transmitter/receiver, an antenna, a virtual master clock processor, and a common data bus. The method of the present invention comprises the inclusion of a node's local clock value in a message just prior to transmission over the network, storage of a node's local clock value in RAM after an incoming message has been received, and the calculation of the time delay between the sending node and the receiving node by the virtual master clock processor. The virtual master clock processor utilizes this time delay in maintaining a virtual master clock value, which it uses in adjusting the value of the node's local clock at periodic intervals. This synchronizes the receiving node to the virtual master clock value. If the magnitude of the time delay exceeds a maximum allowed value, the magnitude is clamped to the maximum allowed value, thereby maintaining synchronization within a predetermined tolerance. A node can receive a message transmitted over the FHSS LAN regardless of the message address. Synchronization is therefore maintained without requiring a node to be able to communicate with any specific node within the FHSS LAN group.

Practical uses of synchronized clocks in distributed systems

Abstract: Synchronized clocks are interesting because they can be used to improve performance of a distributed system by reducing communication Since they have only recently become a reality in distributed systems, their use in distributed algorithms has received relatively little attention This paper discusses a number of distributed algorithms that make use of synchronized clocks and analyzes how clocks are used in these algorithms

System for decoupling clock amortization from clock synchronization

Abstract: A method for accommodating frequent discrete clock synchronization adjustments while maintaining a continuous logical clock time that amortizes the adjustments at a predetermined rate. Two distinct logical clocks are used to decouple clock synchronization procedures from adjustment amortization procedures. One logical clock is discretely synchronized to an external time reference and a second logical clock is adjusted with amortization to provide a continuous monotonically non-decreasing logical clock time.

Synchronous/asynchronous clock net with autosense

Abstract: A circuit within a bus bridge operating in a first clock domain and a second clock domain, wherein the circuit allows data, address or any other information to be reliably transferred between the first and second clock domains regardless whether or not an internal bus clock of the second clock domain is operating in a synchronous or asynchronous fashion, while the circuit still minimizes clock skew between the internal bus clocks of both clock domains as well as any corresponding external bus clocks.

Adaptive clock generation with pseudo random variation

Abstract: Adaptive clock generator including a master clock. A control means detects the current operating mode and, in response, provides a corresponding integer output N. A programmable pulse generator provides an output clock signal comprising a "high" pulse having a predetermined width followed by a "low" pulse having a width of N master clock periods. A dithered clock signal may be provided when the control means provides an integer output N selected from a set of integer values. Preferably, N is selected in a random or pseudo-random manner.

Slave bus controller circuit for class A motor vehicle data communications

Abstract: A Class A node comprising a slave bus controller circuit (SBCC) operates as a remote input/output device for performing Class A communications for a master Class B node over an interconnecting SAE J1850 or similar network (104). The SBCC (102) receives messages from one or more Class B nodes to receive output data which appear at one or more output ports of the SBCC. Output data may be directly provided or may be combined with mask data such that only mask selected bits of the output data are passed to the one or more output ports of the SBCC. Input data directly connected to one or more input ports of the SBCC are transmitted back to a master node as an in-message response of the network. The SBCC provides inexpensive Class A communications using the SAE J1850 protocol which is primarily intended for Class B communications. The SBCC is inexpensive because of its simplified circuitry, its ability to operate without a controlling processor and, in some embodiments, the implementation of its master clock as an RC oscillator (182) which does not directly determine bit timing for the SBCC but is used to measure the bit timing of the master node from which it is receiving messages.

Apparatus for writing data to and reading data from a multi-port RAM in a single clock cycle

Abstract: A clock generator generates repetitive master clock pulses, each master clock pulse having a leading edge and a trailing edge. The time interval between the leading edge of a first master clock pulse and the leading edge of a second master clock pulse defines a single clock cycle. A write pulse generating circuit generates write pulses for writing data into a multi-port RAM, and a read pulse generating circuit generates read pulses for reading data from the RAM. When simultaneous reading and writing of data is requested in a particular clock cycle, the leading edge of the write pulse is generated in response to the leading edge of the first master clock pulse before the leading edge of the second master clock pulse. The leading edge of the read pulse is generated after the leading edge of the write pulse, such that the data written into the memory can be read out of the memory during the same clock cycle through a different port with the only common connection being the memory cells.

Apparatus and method for enhancing the performance of personal computers

Abstract: An accelerator board for use in replacing the microprocessor of a computer system board having a system clock. The accelerator board includes a high frequency oscillator which may be stopped and started under the influence of a clock enable signal. The clock enable signal is synchronized with the phase and logic state of the system clock, to form a clock select signal which serves to toggle a clock selector. When a system access is requested, clock enable stops the high frequency oscillator in a specific phase and logic state, and also toggles the clock selector to select the system clock as the clock speed for all accelerator board operations, giving a smooth transfer. When system access is no longer requested, the high frequency oscillator is restarted and is selected by the clock selector for all accelerator board operations. No time delay is encountered in switching from low to high speeds.

Digital pll circuit having signal edge position measurement

Abstract: A ring oscillator has its inverter states in respective inner stages change at a time unit longer than a period of a master clock MCK and is oscillated at a period longer than the period of the master clock MCK. The inverter states of the respective stages of the ring oscillator are captured by a flipflop circuit and a value indicating each of these states is subtracted by a subtractor from numerical figures indicating the inverter states in the respective stages of the ring oscillator as captured at the timing of the master clock MCK by other flipflop circuits. The difference is output as a signal indicating the position of the input signal edge.

Clock synchronizing device in communication network

Abstract: PURPOSE:To improve accuracy by correcting a synchronizing time with a transmission control queuing time required for the transmission of a synchronizing signal to an equipment in which a clock is built in. CONSTITUTION:A CPU 1 of a time management device 11 reads a current time T0 from a master clock 2 and makes the request of transmission of a clock synchronization start signal S1 including the current time T0 to a terminal equipment 12 to a communication controller 3. Simultaneously a tentative clock 14 starts the measurement of an elapsed time T1. The measurement of the tentative clock 14 is stopped when the transmission of the clock synchronization start signal S1 is made possible after the queu of transmission control processing. Then a time calculation means calculates a time T1 to update a clock 6 and sends it to the terminal equipment 12 as the clock synchronization start signal S1. Upon the receipt of the clock synchronization start signal S1 by a communication controller 5, the terminal equipment 12 uses a time revision means to update the time of the clock 6 into the time T1.

Method and apparatus for obtaining data from a data circuit utilizing alternating clock pulses to gate the data to the output

Abstract: A master clock generates master clock pulses having a selected frequency. A data clock generates a first data clock pulse corresponding to the leading edge of each master clock pulse and a second data clock pulse corresponding to the trailing edge of each master clock pulse. The first and second data clock pulses are applied to an input node of the data circuit. The data circuit generates a first data signal at an output node in response to the first data clock pulse and a second data signal at the output node in response to the second data clock pulse. There is a selected delay between the time a data clock pulse is applied to the input node and the time a data signal appears at the output node. First and second memory elements are provided for storing the data signals from the data circuit. A signal storing circuit stores the first data signal in one of the first or second memory element in response to the first data clock pulse and stores the second data signal in the other first or second memory element in response to the second data clock pulse. Gating circuitry is coupled to the first and second memory elements and to the master clock for selectively outputting the first and second data signals in accordance with the state of the master clock signal.

Cross-monitored pair of clocks for processor fail-safe operation

Abstract: A system for operating a pair of microprocessors with independent system clocks while at the same time providing synchronization by a common interrupt signal, and in which the system clocks are cross-monitored to thereby provide Fail-Safe operation.

Adapter for the connection to a clear-channel telecommunication network

Abstract: An adapter having a line interface circuit for providing an analog attachment to a network (100). The line interface circuit is provided with a reset input for beginning a resynchronization of the timing of the adapter. The adapter further includes a Digital Phase-locked Loop device DPLL (203) driven by a master clock (306) which provides the timing and synchronization signals to the line interface circuits (201). The DPLL (203) divides a master clock down to an internal INT clock (309), a phase comparator (303) compares the INT clock with a reference signal (302) which is synchronized with the receive clock (202) extracted from the line by line interface (201). The phase comparison process operates with a Correction Signal (CS) which has a window centered around the falling edge of the INT clock. A frequency correction is initiated when the reference clock falls outside of the correction window and is achieved by inserting or suppressing a master clock pulse at this time. The adapter further includes means for resetting the line interface circuits and the DPLL at the power-on of the adapter, such that the frequency correction apparatus of the adapter causes two adapters attached at separate ends of a transmission medium to evolve toward stable timing states with respect to each other.

Apparatus for synchronizing asynchronous circuits for testing operations

Abstract: An apparatus for synchronizing a plurality of asynchronous circuits during testing operations is provided. The apparatus includes first and second clock inputs, a test mode input, and an output. The apparatus receives a first clock signal from a first clock at the first clock input, and a second clock signal from a second clock at the second clock input. Responsive to the state of a test mode signal at the test mode input, the apparatus generates either the first clock signal or the second clock signal at the output. A first circuit is arranged to be driven by the output of the apparatus, while a second circuit is driven by one of the first or second clocks. Consequently, the first and second circuits are driven by different clocks when the test mode signal is in one state, and driven by the same clock when the test mode signal is in another state. Because the first and second circuits are driven by the same clock during testing operations, the timing of the communications between the circuits is predictable, making it possible to perform certain testing techniques that are not possible when the timing of inter-circuit communication is not predictable.

Multiple-channel fault-tolerant clock system

Abstract: A fault-tolerant clock having at least four channels, each providing its own clock output, and yet all clock output signals of all functioning channels being coherent with one another. One clock functions as a master with the other clocks of the remaining channels slaving themselves to that one clock. In view of a failure of the master, another clock reigns as the master clock to slave the remaining clocks. If the next master clock fails, then still another clock becomes a master to slave the remaining clock or clocks. The clocks are independently powered such that complete failure of one clock, including its power, does not necessarily prevent the other clocks from providing coherent outputs.

Rationally clocked communication interface

Abstract: An interface controlling digital communication between synchronous systems of unequal clock frequency. A phase locked loop generates one clock Fm from the other Fn by locking the phase of the two clocks at a beating period. Within the beating period, a precompiled set of valid and invalid communication clock cycles for each direction of communication are scheduled into lookup tables. The lookup tables generate outputs to a set of registers for communicating data between the systems of unequal clock frequency.

Audio functional unit and system and method for configuring the same

Abstract: The audio system having a master clock, a serial port clocked according to a serial clock from the audio system, a programmable audio functional circuitry programmable and operable at a plurality of sample rates, and a rate selection control logic which sense a ratio between the serial clock and the master clock. The serial clock is derived from the master clock. The rate selection control logic reprograms the audio functional circuitry based on the ratio, to operate at one of the plurality of sample rates in response to a change in the clock rate of the serial clock, such that the audio functional circuitry operates at another of the plurality of sample rates.

Telemetry data transmission circuit having selectable clock source

Abstract: Disclosed is a telemetry data transmission circuit for a towed hydrophone streamer, the streamer comprised of a plurality of series-coupled modules. The transmission circuit comprises: (1) a slave clock input in a first module capable of receiving a master timing signal from a master clock source located in a second module, the master timing signal capable of synchronizing an operation of the transmission circuit to allow the transmission circuit to place local telemetry data on a data bus coupled to the transmission circuit and running a length of the streamer, (2) a local clock input in the first module capable of receiving a local timing signal from a local clock source located in the first module, the local timing signal alternatively capable of synchronizing the operation of the transmission circuit and (3) a clock source selection circuit capable of allowing the local clock source to synchronize the operation of the transmission circuit as a function of a condition of the master timing signal.

Clock supply apparatus

Abstract: A clock supply apparatus provided in each slave office, wherein a single master clock is received at a clock receiver unit; 0-system and 1-system system clocks are paired and are distributed to the transmission units at terminal ends via a plurality of duplexed clock supply routes; and multistage clock selection units are hierarchically inserted into the duplexed clock supply routes. The system-selection unit for controlling the selection of the 0-system or 1-system at each clock selection unit is given a 0-system and 1-system duplexed structure and is constituted by a system switching command unit for instructing this system-selection.

Digital PLL circuit

Abstract: The invention provides a digital PLL circuit wherein the integration time constant of a random walk filter can be varied adaptively in response to a frequency error A master clock signal having a frequency equal to N (integral number) times that of an input clock signal is normally divided by N by a divider, and the division output of the divider and the input clock signal are compared in phase with each other by a phase comparator The dividing ratio of the divider is temporarily varied in accordance with a result of the comparison so as to make the phases of the division output and the input clock signal coincide with each other to establish synchronism between them A variable step number random walk filter is interposed between the phase comparator and the divider and has a selectively settable integration time constant, and an integration time constant setting circuit varies the step number of the random walk filter in accordance with information of a last phase controlling direction or directions and information of a phase controlling direction at present to vary the integration time constant of the random walk filter

Sound processing digital signal processor

Abstract: PURPOSE: To reduce power consumption by stopping or decelerating the operation of a sound processing digital signal processor when a soundless state is detected. CONSTITUTION: A high speed master clock operating a digital signal processor part 3 by detecting the soundless state of the input sound data is frequency divided to a low period clock, or is stopped. The detection of the soundless state of the input audio data is performed based on a bit clock supplied together with the input data. In such a case, when no bit clock is supplied, the soundless state is judged. Thus, power consumption in the period of the soundless state of the input audio data is reduced, and the power of the digital signal processor itself is saved. COPYRIGHT: (C)1995,JPO

200 mega pixel rate IDCT processor for HDTV applications

Abstract: A high-speed video rate 8 /spl times/ 8 inverse discrete cosine transform (IDCT) processor using a distributed arithmetic architecture is presented 64-point one-dimensional IDCT processing units are simultaneously operated with 8 clock cycles With these 64 fully parallel units and three-stage pipeline structure for each unit, the latency time of this proposed architecture is only 37 cycles ROM banks containing IDCT coefficients are minimized to 12 by applying two pixel bits per clock This VLSI is fabricated in 10-/spl mu/m double metal CMOS process with 120 mm/sup 2/ die area It consumes approximately 3 watts at a 5 volt operating voltage and 50 MHz master clock frequency Since critical path delay is given as 155 nsec, this proposed chip has enough speed for digital HDTV applications >

Time synchronizing method for process monitoring apparatus

Abstract: PURPOSE:To alleviate the load of an LAN bus and to realize the highly accurate time synchronization by synchronizing the time having the large time unit through a local area network(LAN) bus, and synchronizing the time having the smaller unit through the special line for time synchronization. CONSTITUTION:A special line 11 is provided between process monitoring devices in addition to an LAN bus 1. When a slave counter 19 is initialized, a transmitting-station microprocessor 12 gives the instruction to an LAN transmission controller 14 so as to output the time information of year, month, day, hour and minute (a) of a master clock 13. The controller 15 obtains the using right of the LAN bus and transmits the low-precision data when the second unit is within the preset allowable transmission range. Meanwhile, a special-line- transmission controller 15 always sends the data of the units of second and millisecond (b) through the special line 11 for every 1 millisecond. An LAN reception controller 17, which has received the low-precision data, sets the value in the counter 19. During this period, a special-line reception controller 18 sets the data from the transmitting station S1 into the part of second and millisecond (d) in the counter 19.

Phase locked loop circuit

Abstract: PURPOSE:To prevent production of a pseudo clock by comparing a phase of a comparison clock signal with a phase of an output of a frequency divider, applying a phase error signal and a frequency error signal to a VCO so as to make the oscillated frequency close to a prescribed value. CONSTITUTION:A phase comparator 2 compares a phase of a comparison clock signal REF with a phase of an output SD of a frequency divider 9 to output a phase error signal TU and it is inputted to a signal synthesis circuit SM via a switch circuit LP. On the other hand, a frequency phase circuit 3 uses a master clock MC to count a frequency of the output SD and to output frequency error signals FU, FL and they are inputted to the circuit SM and to a gate signal generating circuit GS. The signals TU, FU and TL, FL are sent to a VCO 8 via the circuit SM and a loop filter 7. In this case, while a phase error signal from the comparator 2 is fed to the filter 7, when the frequency error signal is outputted from the comparator 3, the phase error signal is not fed to the filter 7, the oscillating frequency of the VCO approaches a prescribed value to prevent a pseudo clock.

Disk player for changing the playing linear velocity in multiple stages

Abstract: The object of the present invention is to provide a disk player, which is capable of changing the playing linear velocity by multiple stages to shorten the reading time. The disk player comprises includes an optical pick-up for reading data and outputting data signals; a first clock section for generating master clock signals, the first clock section being capable of changing the frequency of the master clock signals by multiple stages; a second clock section for generating second clock signals; a comparing section for comparing frequency and phase of the master clock signals and the second signals and generating deviation signals; and a drive section for sending drive signals, whose voltage level changes according to voltage changes of the deviation signals, to a motor for rotating a disk, whereby the drive section controls the motor so as to synchronize the frequency and the phase of the second clock signals with those of the master clock signals.

Digital phase locked loop circuit

Abstract: PURPOSE:To obtain a digital phase locked loop circuit activated at a high speed with simple circuit configuration in which phase adjustment of a recovered clock signal is easy. CONSTITUTION:A phase comparator 11 compares the phase of a data signal with the phase of a recovered clock signal and outputs a phase error signal. A phase error storage counter 12 receives a phase error signal and outputs a frequency division offset selection signal. A frequency division offset circuit 13 decides a frequency division offset based on a frequency division offset selection signal. A frequency division counter 14 loads the frequency division offset as an initial value, frequency-divides a master clock and outputs a recovered clock signal to obtain a high speed recovered clock signal with simple circuit configuration.

Time registering and scoring apparatus for billiards table games

Abstract: In a game played on a billiards or pool table, a game time is a predetermined time value which is divided between two players or sides as allocated playing time to be counted only whilst a player is at the table. A player's or side's score is reduced according to an amount by which actual playing time overruns allocated playing time during the game time. To this end, time registering and scoring apparatus comprises a master clock (22), first and second player clocks (24, 25), switch means (21) for causing one or other of the player clocks (24, 25) to run with the master clock (22), first and second score store means (26, 27, 28, 29), input keypads (19, 20) for entering data, and digital processing means (30) connected to all these components and incorporating instructions to subtract from the score store means according to an amount by which a player's time used exceeds a predetermined share of a total game time.