Showing papers on "Memory refresh published in 1999"

Universal memory element and method of programming same

Abstract: Method of programming Ovonic memory multistate-digital multibit memory element (14), and use thereof for neural networks and data storage. The device is programmed by applying an energy pulse which is insufficient to switch the memory element from high resistance state to low resistance state, but sufficient to modify said memory material (36) such that accumulation of additional energy pulses causes the memory element to switch from said high resistance state to said low resistance state.

Computational RAM: implementing processors in memory

Abstract: Computational RAM is a processor-in-memory architecture that makes highly effective use of internal memory bandwidth by pitch-matching simple processing elements to memory columns Computational RAM can function either as a conventional memory chip or as a SIMD (single-instruction stream, multiple-data stream) computer When used as a memory, computational RAM is competitive with conventional DRAM in terms of access time, packaging and cost Adding logic to memory is not a simple question of bolting together two existing designs The paper considers how computational RAM integrates processing power with memory by using an architecture that preserves and exploits the features of memory

Parallel decompression and compression system and method for improving storage density and access speed for non-volatile memory and embedded memory devices

Abstract: A flash memory controller and/or embedded memory controller including MemoryF/X Technology that uses data compression and decompression for improved system cost and performance. The Compression Enhanced Flash Memory Controller (CEFMC) of the present invention preferably uses parallel lossless compression and decompression engines embedded into the flash memory controller unit for improved memory density and data bandwidth. In addition, the invention includes a Compression Enhanced Memory Controller (CEMC) where the parallel compression and decompression engines are introduced into the memory controller of the microprocessor unit. The Compression Enhanced Memory Controller (CEMC) invention improves system wide memory density and data bandwidth. The disclosure also indicates preferred methods for specific applications such as usage of the invention for solid-state disks, embedded memory and Systems on Chip (SOC) environments. The disclosure also indicates a novel memory control method for the execute in place (XIP) architectural model. The integrated parallel data compression and decompression capabilities of the CEFMC and CEMC inventions remove system bottle-necks and increase performance matching the data access speeds of the memory subsystem to that of the microprocessor. Thus, the invention allows lower cost systems due to smaller data storage, reduced bandwidth requirements, reduced power and noise.

Dual interface memory card and adapter module for the same

Abstract: A dual interface memory card and an adapter module for the memory card are disclosed to convenient transfer data between the memory card and a computer. The dual interface memory card has a memory unit and a micro control unit connected to the memory unit. The micro control unit includes a USB interface for connecting to a computer whereby the computer is able to read data from and write data to the memory unit, and a host interface for connecting to an electronic product which has the memory card installed therein such that data output from the electronic product can be stored in the memory unit. The adapter module is provided to conveniently connect the dual interface memory card to the computer.

System and method for managing system memory and/or non-volatile memory using a memory controller with integrated compression and decompression capabilities

Abstract: An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high-speed system peripheral bus such as the PCI bus and couples to system memory. The IMC preferably uses a lossless data compression and decompression scheme. Data transfers to and from the integrated memory controller of the present invention can thus be in either of two formats, these being compressed or normal (non-compressed). The IMC also preferably includes microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data from system I/O peripherals such as the hard drive, floppy drive, or local area network (LAN) are decompressed in the IMC and stored into system memory or saved in the system memory in compressed format. Thus, data can be saved in either normal or compressed format, retrieved from the system memory for CPU usage in normal or compressed format, or transmitted and stored on a medium in normal or compressed format. Internal memory mapping allows for format definition spaces which define the format of the data and the data type to be read or written. Software overrides may be placed in applications software in systems that desire to control data decompression at the software application level. The integrated data compression and decompression capabilities of the IMC remove system bottlenecks and increase performance. This allows lower cost systems due to smaller data storage requirements and reduced bandwidth requirements. This also increases system bandwidth and hence increases system performance. Thus the IMC of the present invention is a significant advance over the operation of current memory controllers.

Memory apparatus for vehicle information data

Abstract: A memory apparatus for vehicle information is provided in which the image data of the vehicle's condition in a traffic accident, a traffic offense, a drive condition from the occurrence of an accident to the vehicle's stop after the accident, and a sensor data are memorized and held in a flash memory repeatedly. The memory apparatus enables an analysis of an accident with high precision upon the reproduction of the data of the vehicle's condition, and can be used to provide evidence relating to a traffic offense. The image signals from a CCD camera 1, a RAM 12 for memorizing the sensor's information from a vehicle speed sensor 3, a steering angle sensor 4, a brake pressure sensor 5, and an acceleration sensor 6, and a flash memory 13 for permanently memorizing the signals of the RAM 12, are controlled through a CPU 11. The record information of the RAM 12 is transferred to the flash memory 13 based on the operation of a collision sensor 2 to memorize and hold the information. Moreover, the signal of the flash memory 116 is converted into a video signal to output the information during a reproduction.

Single-electron memory for giga-to-tera bit storage

Abstract: Starting with a brief review on the single-electron memory and its significance among various single-electron devices, this paper addresses the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature operation; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture; device-to-device variations; read/write error rate; and CMOS/single-electron-memory hybrid integration and its positioning among various memory architectures.

Single-electron memory for giga-to-tera bit storage : Special issue on quantum devices and their applications

Abstract: Starting with a brief review on the single-electron memory and its significance among various single-electron devices, this paper addresses the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature operation; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture; device-to-device variations; read/write error rate; and CMOS/singte-electron-memor hybrid integration and its positioning among various memory architectures.

Apparatus and method for improving computer memory speed and capacity

Abstract: A method and apparatus for enhancing memory speed and capacity utilizes a set of electronic switches (24) to isolate the computer data bus (2) from the memory chips (16, 32, 34, 36). The apparatus includes one or more multi-sides memory boards (10, 12, 14) with etched leads (30, 42), lands and feed-through. The memory chips may be mounted on either one side or both sides of each board. Connection between the memory board and the motherboard is made by means of a comb of contact fingers (5) or edge-connector which mates with a connector (8) on the motherboard (28). The data lines and address lines of the computer bus are distinct from each other, and routed to the memory board via the edge connector (8). A set of CMOS TTL or FET switches (24) is located adjacent to the comb (5), and are switched on and off by a decoded combination of address, control, or data lines or by a distinct enable line provided by the CPU (3), controller or other decoding means located on the motherboard (28). As a result, only the memory chips actually required for the memory access are switched on, so that the other memory chips are isolated from the data bus (2). Because of this isolation, the capacitance of the non-switched components is not seen by the data bus, resulting in a lower overall capacitance, and a higher inherent memory access.

Method and apparatus for restricting memory access

Abstract: A method and apparatus for restricting memory access includes processing that begins by monitoring memory access requests. When one of the memory access requests is requesting access to restricted memory, determining the mode of operation of the processor. Note that the mode of operation of the processor may be a system special operation (i.e., operations internal to the operation of the computing system that are beyond access of computing system users and programmers), non-system special operations, or a valid response to a restricted memory access request. When the mode of operation is non-system special and the memory access is requesting access to restricted memory, the memory access request is modified. The processing then continues by providing a response in accordance with the modified memory access request.

Apparatus and method for thermal regulation in memory subsystems

Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory module having a plurality of memory devices coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature (actual or estimated) of the memory device. Based on the determined operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

Dynamic graphics and/or video memory power reducing circuit and method

Abstract: An apparatus and method dynamically controls the graphics and/or video memory power dynamically during idle periods of the memory interface during active system modes. In one embodiment, a memory request detector generates memory request indication data, such as data representing whether memory requests have been received within a predetermined time, based on detection of graphics and/or video memory requests during an active mode of the display system operation. A dynamic activity based memory power controller analyzes the memory request indication data and controls the power consumption of the graphics and/or video memory based on whether memory requests are detected.

Use of a two-way stack approach to optimize flash memory management for embedded database systems

Abstract: A method and system for storing data in data blocks of predetermined size in an electronic memory (e.g. FLASH memory), particularly data such as updatable record of database transactions. The FLASH operates logically as two stacks where data is pushed into either end of the memory in alternating cycles. Between each push or write cycle, a garbage collection cycle is performed whereby only the most recent transaction performed on any particular record is preserved at one end of the stack, while the rest of the stack is made available for new data. When database being monitored is written to permanent memory, the entire FLASH is again made available for new data. If the database is periodically backed up to permanent memory, it can be restored to RAM by reducing the copy from the permanent memory and modifying it according to the record of database transactions in the electronic memory.

Method and apparatus for accessing a memory device

Abstract: A device and method for accessing a row of data in a semiconductor memory device in a single operation is disclosed. The device includes a row of latches having a width which matches the width of the memory array in the semiconductor memory device. The device includes precharge and equilibration circuitry associated with the row of latches and the row of sense amplifiers in device, and timing circuitry for controlling the operation of each in performing full page read and write operations. Writing a full row of data from the row of latches into a selected row of memory cells includes the steps of disconnecting the row of sense amplifiers from the reference voltage sources; equalizing voltage levels appearing on the bit lines of the semiconductor memory and the sense amplifiers; connecting a row of memory cells to the bit lines; driving at least one bit line of each pair of bit lines to a voltage level representing the data value stored in the corresponding latch; coupling the sense amplifiers to the reference voltage sources for powering the sense amplifiers; and disconnecting the row of memory cells from the bit lines.

Detecting modification to computer memory by a DMA device

Abstract: A method and computer for executing the method. A CPU is programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation. A main memory divided into pages for management by a virtual memory manager that uses a table stored in the memory. DMA (direct memory access) monitoring circuitry and/or software is designed to monitor DMA memory write transactions to a main memory of a computer by a DMA device of the computer; to detect when the first representation is overwritten by a DMA memory write transaction initiated by the second process, without the second process informing the first process of the DMA memory write transaction, the detecting guaranteed to occur no later than the next access of the second representation following the DMA memory write transaction; to record an indication of a location in the main memory written by the DMA memory write transaction, the DMA monitoring circuitry designed to operate without being informed of the DMA memory write transaction by a CPU of the computer before initiation of the DMA memory write transaction, and to provide the indication to the CPU on request; and to report to the first process that the first representation is overwritten by a DMA memory write transaction. The DMA monitoring circuitry includes a plurality of registers outside the address space of the main memory, each register including an address tag and a vector of memory cells, and control circuitry designed to establish an association between a one of the plurality of registers with a region of the memory when a modification to the region is detected by setting the address tag of the one register to an approximation of the address of the region, and to set the values of the memory cells of the vector to record a fine indication of the address of a memory location modified, the control circuitry being operable without continuing supervisory control of a CPU of the computer. Circuitry is designed to record indications of modification to pages of the main memory into the registers. Read circuitry is designed to respond to a read request from the CPU by providing an address of a modified memory location. The virtual memory management tables do not provide backing store for the modification indications stored in the registers.

Maps: a compiler-managed memory system for raw machines

Abstract: This paper describes Maps, a compiler managed memory system for Raw architectures. Traditional processors for sequential programs maintain the abstraction of a unified memory by using a single centralized memory system. This implementation leads to the infamous "Von Neumann bottleneck," with machine performance limited by the large memory latency and limited memory bandwidth. A Raw architecture addresses this problem by taking advantage of the rapidly increasing transistor budget to move much of its memory on chip. To remove the bottleneck and complexity associated with centralized memory, Raw distributes the memory with its processing elements. Unified memory semantics are implemented jointly by the hardware and the compiler. The hardware provides a clean compiler interface to its two inter-tile interconnects: a fast, statically schedulable network and a traditional dynamic network. Maps then uses these communication mechanisms to orchestrate the memory accesses for low latency and parallelism while enforcing proper dependence. It optimizes for speed in two ways: by finding accesses that can be scheduled on the static interconnect through static promotion, and by minimizing dependence sequentialization for the remaining accesses. Static promotion is performed using equivalence class unification and modulo unrolling; memory dependences are enforced through explicit synchronization and software serial ordering. We have implemented Maps based on the SUIF infrastructure. This paper demonstrates that the exclusive use of static promotion yields roughly 20-fold speedup on 32 tiles for our regular applications and about 5-fold speedup on 16 or more tiles for our irregular applications. The paper also shows that selective use of dynamic accesses can be a useful complement to the mostly static memory system.

Integrated system management memory for system management interrupt handler independent of BIOS and operating system

Abstract: A memory controller with an integrated system management memory region is disclosed. The memory controller receives an SMI acknowledge signal from a processor. The processor then delivers a system management memory address to the memory controller. Instead of fetching SMI handler instructions from the address indicated by the processor, the memory controller instead fetches SMI handler instructions from its integrated system management memory region. At the end of the integrated system management memory's SMI handler, the processor is instructed to fetch instructions from the address originally specified by the processor. In this manner, a BIOS SMI routine may be executed after the integrated SMI routine is executed.

Replacement, upgrade and/or addition of hot-pluggable components in a computer system

Abstract: A computer system adapted for hot-pluggable components such as memory modules that may be replaced, upgraded and/or added without disturbing normal operation of the computer system. A failing memory module may be replaced by copying its contents to a new memory module in a background operation while the computer system runs its operating system and applications programs. When all contents are copied to the new memory module, the failing memory module may be removed without having to shut down the computer system. Computer system memory may be upgraded or added to by inserting the new memory module(s) into vacant disconnected memory connectors, whereupon the computer system automatically recognizes the new memory module(s), synchronously connects the new memory module(s) to the computer system memory bus, initializes the new memory module(s), and then notifies the operating system that the new memory module(s) is available, all without disturbing normal operation of the computer system.

Semiconductor memory device having reduced data access time and improve speed

Abstract: Disclosed is a semiconductor memory device comprising a precharging unit between bit lines within a memory cell region and bit lines within a sense amplifier region, respectively. When performing a column operation on the bit lines within the sense amplifier region upon consecutive read operations, the bit lines within the memory cell region are precharged and a wordline is disabled, and thus the memory cell region comes to the ready to enable a new wordline. Accordingly, the timing of row and column operations can be reduced, thereby reducing a data access time and realizing a high speed operation.

Content addressable memory cell providing simultaneous read and compare capability

Abstract: The need to employ three separate cycles for write, read and compare operations for operation of a content addressable memory cell is obviated by a memory cell architecture that allows simultaneous read and compare operations, thereby reducing memory cycle time by one-third of that of a conventional CAM. To enable the data bit stored in the memory cell to be compared with a reference bit, the memory cell is coupled with a comparator, that receives inputs from the data nodes of the memory cell and a set of comparison bit input lines. Rather than supplying reference data by way of the data lines through which data is written into and read from the memory cell, as in a conventional CAM, the compare bit and its complement are coupled to the match logic exclusively of the memory cell. Since application of the comparison bit does not involve the use of the normal data read and write lines, accessing data read and write paths for the memory cell is not required. As a consequence, a read cycle and a comparison cycle may be performed simultaneously, without one affecting the other.

Memory expansion module with stacked memory packages and a serial storage unit

Abstract: A memory expansion module with stacked memory packages. A memory module is implemented using stacked memory packages. Each of the stacked memory packages contains multiple memory chips, typically DRAMs (dynamic random access memory). The memory may be organized into multiple banks, wherein a given memory chip within a stacked memory package is part of one bank, while another memory chip in the same package is part of another bank. The memory module also includes a clock driver chip and a storage unit. The storage unit is configured to store module identification information, such as a serial number. The storage unit is also configured to store information correlating electrical contact pads on the module with individual signal pins on the stacked memory packages. This may allow an error to be quickly traced to a specific pin on a stacked memory package when an error is detected on the memory bus by an error correction subsystem.

Nonvolatile configuration cells and cell arrays

Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Smart card memory management system and method

Abstract: A system and method for memory management in a smart card are disclosed. The memory manager, preferably part of a true operating system, is the single device by which memory in the smart card is allocated and deallocated. Memory allocation for new data objects and memory deallocation as the result of data object deletion are made by reference to a memory management record, preferably a bitmap, which is stored in RAM and formed upon smart card initialization.

Bit line control circuit for a memory array using 2-bit non-volatile memory cells

Abstract: A bit line control circuit for accessing an array of 2-bit non-volatile memory cells. Each memory cell has a first and a second charge trapping regions. A set of bit lines extends between the array and the bit line control circuit. The bit line control circuit includes pass transistors that selectively route pairs of bit lines to corresponding voltage control circuits in either a first order or a second (reversed) order. This enables both the first and second charge trapping regions of the memory cells to be accessed from the same voltage control circuits. In one embodiment, the bit line control circuit includes a first-level pass transistor coupled to each bit line. A second set of bit lines is coupled to the first-level pass transistors. A parallel-connected pair of second-level pass transistors is coupled to each bit line in the second set of bit lines. A third set of bit lines is coupled to the second-level pass transistors. The voltage control circuits are coupled to the third set of bit lines. The voltage control circuits apply voltages to the third set of bit lines to perform read, write and erase operations in the memory cells of the memory array. The first and second level pass transistors provide a consistent path for accessing all memory cells in the array, as well as handling the edge conditions introduced by the right-most and left-most columns of memory cells.

The processor-memory bottleneck: problems and solutions

Abstract: The rate of improvement in microprocessor speed exceeds the rate of improvement in DRAM (Dynamic Random Access Memory) speed. So although the disparity between processor and memory speed is already an issue, downstream someplace it will be a much bigger one. Hence computer designers are faced with an increasing Processor - Memory Performance Gap [1], which now is the primary obstacle to improved computer system performance. This article examines this problem as well as its various solutions.

High-density nonvolatile memory cell

Abstract: A compact nonvolatile programmable memory cell. The memory cell has a floating gate (118), control gate (123), drain (108), and source regions (112). The memory cell is an electrically erasable programmable read only memory (EEPROM) cell or a Flash memory cell. Data may be stored the memory cell of the present invention for the required lifetime of the memory cell usage, and data is retained even when power is removed. The memory cell of the present invention has a substantially transverse or vertical channel (140), relative to a surface of a substrate. The memory may be used to create very high-density memory arrays.

Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and the memory controller. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A multi-bank refresh scheme is used to cut down the number of collisions between memory refresh operations and memory data access operations. A read buffer is used to buffer read data, thereby allowing memory refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer is used to buffer write data, thereby allowing memory refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. Both the read buffer and the write buffer can be constructed of DRAM cells.

SRAM controller for parallel processor architecture including address and command queue and arbiter

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Method and apparatus for analyzing a main memory configuration

Abstract: A method and apparatus for analyzing the configuration of a computer main memory. A complex memory controller, which imposes restrictions on the memory's configuration, determines whether a user-selected configuration is consistent with those restrictions. The results of the determination are then reported to the user. The results may also be used to program the memory controller.