Showing papers on "Memory refresh published in 2004"

Multi-state memory

Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Flash memory data correction and scrub techniques

Abstract: In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.

Hybrid non-volatile memory system

Abstract: The present invention presents a hybrid non-volatile system that uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit the relative advantages of each these technology with respect to the others. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data used by the control to manage the storage of host data in the flash memory. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the to the memory or read back to the host.

Memory controller for non-homogeneous memory system

Abstract: A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.

Detecting over programmed memory

Abstract: In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.

Semiconductor memory cell and method of forming same

Abstract: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

4-Mb MOSFET-selected phase-change memory experimental chip

Abstract: This paper presents a 4-Mb phase-change memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-/spl mu/m CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to present NOR Flash memories. Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone phase-change memory with standard CMOS fabrication process.

Integral memory buffer and serial presence detect capability for fully-buffered memory modules

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, a serial presence detect function is included within a memory module buffer instead of being provided by a separate EEPROM device mounted on the memory module. Various embodiments thus can provide cost savings, chip placement and signal routing simplification, and can in some circumstances save pins on the module. Other embodiments are described and claimed.

Method and system for reducing the peak current in refreshing dynamic random access memory devices

Abstract: A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset code, to delay the initiation of a received auto-refresh or self-refresh command. A large number of dynamic random access memory devices in a system may be provided with different delay values and possibly offset codes so that the memory device do not all perform refreshes simultaneously in response to an auto-refresh or self-refresh command issued to all of the memory devices simultaneously. As a result, the peak current drawn by the memory devices resulting from the auto-refresh command or self-refresh command is maintained at a relatively low value.

Flash memory system startup operation

Abstract: Multiple copies of firmware code for controlling operation of a non-volatile flash memory system are stored at different suitable locations of the flash memory of a memory system. A map of addresses of these locations is also stored in the flash memory. Upon initialization of the memory system, boot code stored in the memory controller is executed by its microprocessor to reference the address map and load one copy of the firmware from the flash memory into a controller memory, from which it may then be executed by the microprocessor to operate the memory system to store and retrieve user data. An error correction code (ECC) is used to check the data but the best portions of the two or more firmware copies stored in the flash memory are used to reduce the need to use ECC. The firmware code may be stored in the flash memory in two-states when user data is stored in the same memory in more than two-states.

Memory access system and method using de-coupled read and write circuits

Abstract: A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.

External memory device to provide disk device and optical functionality

Abstract: A memory device is attachable to a host computer system. The memory device includes an interface to couple the memory device to the host computer system. The memory device includes a controller for controlling operations in the memory device. The controller enables a first mode of operation in which the memory device communicates with the host computer system through the interface by emulating a disk device and a second mode of operation in which the memory device communicates through the interface by emulating an optical device.

SDRAM memory device with an embedded NAND flash controller

Abstract: A memory device (86) includes two dies. A first memory (76) is fabricated on one die (74). A controller (78) of the first memory (76) is fabricated on the other die (72) Also fabricated on the other die (72) is another component, such as a second memory (80), that communicates with a host system using a plurality of signals different from the signals used by the first memory. The device includes a single interface for communicating with the host system using only the respective signals of the second component. In a most preferred embodiment, the first memory (76) is a NAND flash memory and the second memory (80) is a SDRAM.

Methods and apparatus to update information in a memory

Abstract: A method and apparatus to update information in a memory is provided. The apparatus may be a nonvolatile memory that may include a control circuit to swap the physical addresses of a first block and a second block of the nonvolatile memory as part of an operation to update information stored in the first block, wherein the control circuit is internal to the nonvolatile memory. Other embodiments are described and claimed.

Nonvolatile semiconductor memory device and control method thereof

Abstract: A nonvolatile semiconductor memory device includes a memory array in which a plurality of memory cells are arranged in a row direction and a column direction, each of the memory cells being formed by connecting one end of a variable resistive element for storing information according to a change in electric resistance caused by an electric stress and a drain of a selection transistor to each other on a semiconductor substrate, a voltage switch circuit for switching among a program voltage, an erase voltage and a read voltage to be applied to the source line and the bit line connected to the memory cell, and a pulse voltage applying circuit. In the state where the program voltage or erase voltage corresponding to the bit line and the source line is applied to the bit line and the source line connected to a memory cell to be programmed or erased in the memory array via the voltage switch circuit, the pulse voltage applying circuit applies a voltage pulse for programming or erasing to the word line connected to the gate electrode of the selection transistor connected to the memory cell.

Semiconductor memory cell, array, architecture and device, and method of operating same

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell (FIG. 3A, 3B) includes two transistors (102a, 102b) which store complementary data states (“0”, “1”). That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary '0') and the other transistor of the memory cell stores a logic high (a binary “l”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell (FIG. 4). That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

A study of performance impact of memory controller features in multi-processor server environment

Abstract: With the growing imbalance between processor and memory performance it becomes more and more important to optimize the memory controller features to obtain the maximum possible performance out of the memory subsystem. This paper presents a study of the performance impact of several memory controller features in multi-processor (MP) server environments that use a DDR/DDR2 based memory subsystem. The results from our studies show that significant performance improvements can be obtained by carefully optimizing the memory controller features. For instance, one of our studies shows that in a system with an in-order shared bus connecting the CPUs and memory controller, an intelligent read-to-write switching memory controller feature can provide the same order of benefit as doubling the number of interleaved memory ranks. Another study shows that much lower average loaded read latency across a wider range of throughput can be obtained by a delayed write scheduling feature.

Non-volatile memory and control with improved partial page program capability

Abstract: In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.

Status and outlook of emerging nonvolatile memory technologies

Abstract: This paper reviews the concept, status and challenges of emerging nonvolatile memory technologies. The technologies that are discussed and compared to state of the art flash technology are the conductive bridging RAM (CBRAM), the ferro-electric RAM (FeRAM), the magneto-resistive RAM (MRAM), the organic RAM (ORAM) and the phase change RAM (PCRAM).

Power management using a pre-determined thermal characteristic of a memory module

Abstract: A computer system includes a memory module. Power management in the computer system is performed with at least one temperature rise parameter (ΔTx) of the memory module.

System and method for thermal throttling of memory modules

Abstract: Some embodiments of the invention accurately account for power dissipation in memory systems that include individual memory modules by keeping track of the number of read requests, the number of write requests, and the number of activate requests that are applied to the individual memory modules during selected time periods If the sum of these totals exceeds a threshold level, the embodiments throttle the memory system, either by throttling the entire memory system based in response to the most active memory module, or by throttling individual memory modules as needed Other embodiments of the invention may assign the same or different weights to activate requests, read requests, and write requests Other embodiments are described and claimed

Method and apparatus for booting a computer system

Abstract: A method for quickly booting a personal computer system using a non-volatile reprogrammable memory device. A compressed memory image of the contents of the system working memory when the system is in a desired operational state is stored in the non-volatile reprogrammable memory. The image can be captured during a set-up process, or when the computer system is shut down. When the user restarts the computer, the memory image is decompressed and loaded into the working memory. This places the computer in an operational state in a very short space of time.

Flash memory system with a high-speed flash controller

Abstract: A multi media card (MMC) is disclosed. The MMC includes a flash controller and at least one flash memory device. The flash controller increases the throughput of the at least one flash memory device to match the speed of a host bus coupled to the MMC. The flash controller increases the throughput by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device, increasing the width of a memory data bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing a write-cache memory write operation, and any combination thereof.

Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)

Abstract: The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a memory rank selection signal (r), wherein the memory rank decoder generates the memory rank selection signal (r) in response to external selection signals applied to the dual inline module (DIMM).

Memory devices, systems and methods using selective on-die termination

Abstract: A memory system includes first and second memory devices having commonly connected data terminals and commonly connected memory control signal terminals, e.g., devices in respective first and second independently selectable memory banks that share common data lines and common memory control signal lines, such as column address strobe, row address strobe, write enable, and address signal lines. The first and second memory devices includes respective selective on-die termination (ODT) circuits configured to selectively provide first and second termination impedances at their respective data terminals responsive to a memory control signal at the commonly connected memory control signal terminals. The selective ODT circuits may produce the first termination impedance responsive to a memory write operation, and may produce the second termination impedance responsive to a memory read operation and/or expiration of a predetermined time interval following termination of the memory write operation. Preferably, the first termination impedance is less than the second termination impedance, and the selective ODT circuits provide the first termination impedance responsive to the memory write operation irrespective of which of the first and second memory devices is being written to.

Non-Volatile Memory and Method With Bit Line to Bit Line Coupled Compensation

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Low power programming technique for a floating body memory transistor, memory cell, and memory array

Abstract: The present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State '0' in a memory cell employing an electrically floating body transistor). In this regard, the present invention programs a logic low or State '0' in the memory cell while the electrically floating body transistor is in the 'OFF' state or substantially 'OFF' state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

Memory device having staggered memory operations

Abstract: A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.

Booting from non-volatile memory

Abstract: A computer system includes a system memory (SM) and a non-volatile memory (NVM). The computer system is arranged to copy at least a part of the system state, stored in the system memory during a clean boot-up procedure, into the non-volatile memory (209, 329). During subsequent start-ups of the computer system, the system state is copied from the non-volatile memory into the system memory (205, 305), resulting in a significantly faster system start-up. In case the configuration of the computer system has changed, the complete boot-up procedure is executed again and the new system state is copied into the non-volatile memory, overwriting the previously stored system state.

Data writing method for semiconductor memory device and semiconductor memory device

Abstract: A semiconductor integrated circuit device includes a first data transfer line electrically connected to a first memory cell block, a second data transfer line electrically connected to a second memory cell block, a charge circuit which charges any one of the first and second data transfer lines, a first data store circuit, second and third data store circuits electrically connected to the first data store circuit, a charge/discharge circuit which charges or discharges a voltage node on the basis of the data held in the third data store circuit, a first connecting circuit which electrically connects the voltage node to any one of the first and second data transfer lines, a fourth data store circuit, and a second connecting circuit which electrically connects the fourth data store circuit to the voltage node.