Showing papers on "Metal gate published in 1982"

Charge accumulation and mobility in thin dielectric MOS transistors

Abstract: A study of the turn-on of very thin dielectric MOS devices from subthreshold to strong inversion is described. A functional form has been found for the derivative of channel charge with respect to gate voltage, the derivative of channel charge with respect to distance along the channel, and the electric field along the channel in this transition region. A method to extract electron mobility versus gate voltage independent of any arbitrarily defined threshold voltage has been shown. Measured data on the electron mobility vs gate voltage for 100A gate dielectric MOS devices are reported.

Method of operating a semiconductor memory circuit

Abstract: Disclosed is a semiconductor memory element having a semiconductor substrate of P conductivity type, source and drain regions which are of N conductivity type and formed in the substrate, a first gate insulation layer formed on the major surface of the substrate, corresponding to a channel region located between the source and drain, a floating gate electrode formed on the first gate insulation layer so as to partially overlap the channel region, a second gate insulation layer formed on the floating gate electrode, a control gate electrode formed on the second gate insulation layer so as to partially overlap the floating gate electrode, and an addressing gate electrode formed on the control gate electrode, extending to a portion of the channel region not covered by the floating gate electrode and the control gate electrode.

Offset-gate chemical-sensitive field-effect transistors (OG-CHEMFETS) with electrolytically-programmable selectivity

Abstract: A selective chemosensitive microelectronic transducer is provided for the detection and measurement of chemical properties, by engineering a field-effect transistor such that source 6 and drain 7 regions are connected to bonding pads 2 and 4, and the semiconductor bulk connected to pad 1. The metal gate 8 is extended laterally to a remote area 9, and also to bonding pad 3 via a narrow metallization track 5 designed to support only a limited, predetermined electrical current in the manner of a fusible link. External electrical access to the device is achieved with wirebonding 14, and the device is selectively sealed with an inert, impervious encapsulation material 10 such that only gate area 9 remains exposed. Electroactive materials are deposited over the offset-gate area 9, or electrodeposited using connection through 8, 5 and 3. Subsequently, link 5 is open-circuited by pulsed electrical overload, creating a floating chemosensitive gate.

Method of manufacturing a self-aligned U-MOS semiconductor device

Abstract: A method of manufacturing a MOS semiconductor device, which comprises a step of forming a groove in a predetermined portion of a semiconductor substrate, a step of forming a gate insulation film to cover the entire surface of the substrate inclusive of the groove, a step of depositing a gate electrode material to a thickness greater than one half the width of the opening of the groove to thereby fill the groove with the gate electrode material, and a step of forming a gate electrode within the groove by etching away the gate electrode material until the gate insulation film other than that within the groove is exposed. Before the step of etching the gate electrode material, a portion of the gate material layer including a portion thereof over part of the groove and/or a portion of the layer other than that within the groove may be covered with a mask material to simultaneously form a lead integral with the gate electrode within the groove and/or a separate gate electrode at the time of the etching of the gate electrode material.

EPROM Cell with high gate injection efficiency

Abstract: An n-channel erasable and programmable read-only memory (EPROM) with very high gate injection efficiency is described, which we call a perpendicularly accelerating channel injection MOS (PACMOS). PACMOS has a dual gate structure arranging a select-gate and a floating gate in series between the source and drain. The select-gate and the floating gate are biased as to conduct the source and the drain potentials into two channels under the respective gate. The channel injection utilizes a channel potential gap built in at the boundary of these two channels. A fabricated PACMOS has shown that it can be programmed by voltage of 8V and current of 0.15µA, where a total injection efficiency (gate current /drain current) amounts to 10-3. It is considered that this very high gate injection efficiency is brought by the electron attractive field in the gate oxide under the floating gate.

MOS Semiconductor device and method of manufacturing the same

Abstract: An MOS semiconductor device, wherein a buried region of silicon oxide or silicon nitride extends partly over the bottom plane of the channel region of an MOS transistor.

Method of fabricating an integrated circuit voltage multiplier containing a parallel plate capacitor

Abstract: Disclosed is a process which is fully compatible with normal two layer polysilicon SNOS process and provides polysilicon parallel plate capacitors and silicon gate non-memory MOS transistors (diodes) for constructing therefrom an on-chip, dual polarity high voltage multiplier. From the polysilicon I layer deposited over a gate oxide, the polysilicon I resistor, the non-memory device gate and the capacitor lower plate are formed. Then, the resistor, non-memory device gate and active region and the periphery of the capacitor lower plate are covered with an isolation oxide. Next, a dielectric, e.g., oxide-nitride, and polysilicon II layers are formed over the structure. Polysilicon II is patterned into interconnect, gate for SNOS memory device and capacitor upper plate, the latter having a plurality of holes therein. The dielectric is formed into SNOS device gate insulator and the capacitor insulator, the latter having holes in registration with the holes in the capacitor upper plate. Finally, by thermal diffusion of active impurities, all gates, interconnect and both capacitor plates are doped and all sources and drains for memory and non-memory devices formed.

Ammonia-Annealed SiO2Films for Thin-Gate Insulator

Abstract: Thermal nitridation of a thin SiO2 film in purified NH3 gas at elevated temperatures produces a strong protective layer against impurity diffusion. This enables fabrication of a reliable MOS structure with a high work function gate material such as p+ polysilicon. This combination is advantageous for miniaturized MOSFETs because a reasonable threshold voltage is obtainable without a high dose of channel ion implantation which deteriorates carrier mobilities and interfacial properties. Experimental results indicate easy incorporation of a nitrified SiO2 film in the conventional MOS process.

Method of fabricating semiconductor devices using laser annealing

Abstract: In the manufacture of VLSI (very large scale integrated) MOS (metal-oxide-semiconductor) circuits, a polysilicon gate is deposited on an oxide layer overlaying a silicon substrate. Ideally, the polysilicon gate is made extremely small and with sharply defined vertical boundaries. The invention proposes depositing a polysilicon layer, covering a region of the layer with an antireflective coating, and laser annealing the layer. Laser radiation is absorbed to a higher level by the coated region than elsewhere and consequently the polysilicon layer in this region melts and recrystallizes into large grains. The polysilicon layer is then etched using etch conditions ensuring preferential etching of unrecrystallized polysilicon in comparison with recrystallized polysilicon. Consequently, except at the coated region, the polysilicon is etched quickly and there is very little undercutting of the gate region. Preferential etching methods based on differing dopant levels in polysilicon are known but do not produce the sharp edge definition enabled using the present process.

Stacked MOS transistor

Abstract: In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part (18, 20, 22) formed in a silicon substrate (12) and an upper part (30, 32, 26) composed of recrystallized polysilicon. The device gate (24) is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.

Semiconductor integrated circuit devices with protective means against overvoltages

Abstract: An additional N + region is provided in a P type substrate adjacent to a protective N + resistor region with an insulating layer and metal layer interposed between the N + region and the N + resistor region. The N + resistor region, the oxide layer, the polysilicon layer and N + region constitute an MOS transistor, respectively corresponding to a drain region, a gate insulating layer, a gate electrode and a source region of the MOS transistor. When a very high excessive voltage that otherwise would destroy the PN junction between the substrate and the resistor region is applied to the input terminal, the MOS transistor is rendered conductive and the excessive voltage is absorbed.

Nonvolatile MOS memory cell with tunneling element

Abstract: A nonvolatile memory cell (16) is fabricated on a substrate (12) and includes a source region (46) and drain regions (48, 50 and 52). Step oxides (40, 42 and 44) are fabricated respectively over the regions (46, 48 and 52). A gate oxide (58) is formed between the step oxides (40 and 42). A thin oxide tunneling element (74) is fabricated between the step oxides (42, 44) and over the drain region (50). A floating gate (38) comprising a polysilicon layer is fabricated over the step oxides (40, 42, 44), the gate oxide (58) and the tunneling element (74). An insulation layer (36) is fabricated over the floating gate (38). Finally, a control gate (34) is fabricated over the insulating layer (36) to provide capacitive coupling to the floating gate (38). The nonvolatile memory cell (16) has enhanced capacitive coupling between the control gate (34) and the floating gate (38) while it has a minimum of capacitive coupling between the floating gate (38) and the source and drain regions (46, 48, 50, 52) in the substrate (12).

Minimal mask process for manufacturing insulated-gate semiconductor devices with integral shorts

Abstract: Processes for manufacturing insulated-gate semiconductor devices such as MOSFETs wherein the source and base regions and the source-to-base ohmic short are formed employing self-aligned masking techniques are disclosed. In the exemplary case of a MOSFET, the processes begin with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. Through subsequent masking and etching steps, channels are etched through the polysilicon gate layer at least to the drain region. The un-etched portions define polysilicon gate electrodes spaced along the drain region. A two-stage polysilicon etch procedure is disclosed. An initial etch step produces relatively narrow channels. Unetched portions of the polysilicon layer are then used as masks to form a shorting extension of the device base region, preferably by ion implantation. In a subsequent lateral etch step, previously un-etched portions of the polysilicon gate electrode layer are etched to define insulated polysilicon gate electrode structures extending upwardly from and spaced along the principal surface. MOSFET source and base regions are then formed, preferably by vertical ion implantation, employing the polysilicon gate electrode structures as masks. Appropriate electrode metallization is applied.

Reduction of gate oxide breakdown for booted nodes in MOS integrated circuits

Abstract: In a clock generator circuit for a dynamic RAM or the like it is necessary to boot certain nodes to a value to above the supply voltage in order to provide a high-level gate voltage for output transistors. To prevent excess voltage on the gate oxide of a transistor connected to a booted node, a series transistor is added which has the supply voltage on its gate, so neither transistor will have the full booted voltage across its gate oxide.

MOSFET buffer circuit with an improved bootstrapping circuit

Abstract: A semiconductor circuit has first and second MOS transistors which are connected between an output terminal and a positive and a reference power source terminal, respectively, a bootstrap capacitor connected between the output terminal and the gate of the first MOS transistor, an inverter which inverts the input signal and which supplies the inverted signal to the gate of the second MOS transistor after a predetermined delay timne, and a switching MOS transistor having a current path connected between the input terminal and the gate of the first MOS transistor. The switching MOS transistor has a threshold voltage greater than that of the second MOS transistor.

Method for producing integrated MOS field effect transistors with an additional track level of metal silicides

Abstract: A method for producing integrated MOS field effect transistors, particularly complementary MOS field effect transistor circuits (CMOS-FET's) is provided wherein a metal silicide level, comprised preferably of tantalum silicide, is utilized as an additional interconnect (11). In this manner, all contact areas (9, 10, 13, 14, 15) to active (MOS) regions (6, 7) and polysilicon regions (5) for the metal silicide level (11) and also for the metal interconnect (12) are opened before the precipitation of the metal silicides. The structuring of the metal silicide level (11) is executed in such a manner that the p + regions of the circuit remain protected during a flow-spread of an intermediate oxide (17) comprised of phosphorous glass.

Polysilicon oxidation self-aligned MOS (POSA MOS) — A new self-aligned double source/drain ion implantation technique for VLSI

Abstract: A new MOS device named polysilicon oxidation self-aligned (POSA) MOS is proposed to enhance device performance for VLSI circuits. The device characteristics revealed significant improvement in hot-electron effects, short-channel effects and punch through voltage.

Manufacture of thin film transistor

Abstract: PURPOSE:To accelerate the operating speed of a transistor by coating a negative type resistor film and forming source and drain regions at gate electrodes by the exposure from the surface of a substrate, thereby micromiaturizing an element CONSTITUTION:After an opaque metal gate electrode 42 is formed on a transparent insulating substrate 41, a gate insulating film 43 and a P type thin semiconductor film 44 are sequentially accumulated on the overall surface Thereafter, an insulating film 45 is accumulated, a negative type resist film 46 is coated on the film, the entire surface is exposed by a visible light 47 from the back surface of a substrate 41, patterned, the film 45 is etched, a resist pattern self-aligned with the electrode 42 is formed, an ions 48 are implanted to form an n type source region 49 and drain region 50 Then, the films 46, 45 are removed, an insulating film 51 is formed on the overall surface, contacting holes are opened at the film, source and drain electrodes 52, 53 are arranged, thereby completing an n-channel thin film transistor

Fringing Field Effect in MOS Devices

Abstract: Fringing field action in metal-oxide-semiconductor (MOS) devices is discussed theoretically. Line capacitance coefficients on silicon-on-sapphire (SOS) and bulk configurations are determined from a three-dimensional model. Increase of threshold voltage of narrow-width devices due to fringing is described.

Semiconductor memory and method of producing the same

Abstract: A static RAM using a flip-flop circuit as a memory cell is disclosed. The gate oxide film of the MOS transistor for selecting the memory cell is thicker than the gate oxide film of the MOS transistor included in the peripheral circuit of the memory matrix.

Field effect semiconductor device and method of manufacturing such a device

Abstract: A field effect semiconductor device has a substrate (11) of a compound semiconductor in which an active region (15) is formed. A gate electrode (16) is formed on the active region. The gate electrode (16) comprises silicon and at least one refractory metal, but the composition of the gate electrode (16) varies through its thickness. For example, the gate electrode (16) is formed from a double layer (16A, 16B) structure in which the lower layer (16A) has a higher etching rate than the upper layer (16B). After etching, the portion of the gate electrode (16) which contacts the active region (15) is shorter than the portion of the gate electrode (16) remote from the active region (15). Thus a gate length of less than 1 micrometer can be provided. Alternatives to the double layer (16A, 16B) structure for providing gate electrode (16) can be used. In each alternative, composition of the gate electrode (16) varies through its thickness so that different levels of the gate electrode (16) are subject to different etching rates. Methods of manufacturing such a field effect semiconductor device are described.

Surface induced latch-up in vlsi cmos circuits "1

Abstract: by using appropriate test structures. The basic test structure consisted of the latch-up sensi- te influence on latch-up in CMOS with and without tionally provided with a field oxide metal gate epitaxy are presented. as shown in Fig. 1. Latch-up was initiated by While in ChOS without epitaxy latch-up is bulk initiated, in structures with an epitaxial layer latch-up is essentially surface controlled. The critical latch-up current in this case is two orders of magnitude higher. The strong surface effect observed is a consequence of the gate in- fluence on avalanche breakdown, on surface conduc- tion of the field oxide MOSFET's and on current gains of the bipolar transistors. nel effects of the field oxide transistors imply the most severe limitations for latch-up immuni- ty * Experimental and simulated results of the ga- tive part of the conventional CMOS inverter addi-

Offset-gate chemical-sensitive field-effect transistors (OG-CHEMFETs)

Abstract: A selective chemosensitive microelectronic transducer is provided for the detection and measurement of chemical properties, by engineering a field-effect transistor such that source (6) and drain (7) regions are connected to bonding pads (2 and 4), and the semiconductor bulk connected to pad (1). The metal gate (8) is extended laterally to a remote area (9), and also to bonding pad (3) via a narrow metallization track (5) designed to support only a limited, predetermined electrical current in the manner of a fusible link. External electrical access to the device is achieved with wire-bonding (14), and the device is selectively sealed with an inert, impervious encapsulation material (10) such that only gate area (9) remains exposed. Electroactive materials are deposited over the offset-gate area (9), or electrodeposited using connection through (8, 5 and 3). Subsequently, link (5) is open-circuited by pulsed electrical overload, creating a floating chemosensitive gate.

Manufacture of nonvolatile semiconductor memory storage

Abstract: PURPOSE:To obtain the memory, in which the thresholds of each section of a channel region are accurate, by forming a floating gate onto a semiconductor substrate through a gate insulating film, implanting impurity ions of the same conduction type as the substrate to the surface of the substrate under the floating gate through said gate and forming a control gate extending over a region, in which there exists no floating gate, from the upper section of the floating gate through a gate insulating film. CONSTITUTION:The floating gate 13 consisting of a polycrystalline Si film of a predetermined pattern is formed onto the p type Si substrate 11 through the first gate oxide film 121, and boron ions are implanted in the whole surface containing the gate 13 to form an ion implantation layer 14. Accordingly, the implantation layer 14 is formed to a shape that is shallow under the gate 13 and is deep in regions except a section under the gate 13, and the control gate 15 using polycrystalline Si is formed while coating the gate 13 through the second gate oxide film 122 and an extension section from the gate 13. Arsenic ions are implanted while using the gate 15 as a mask, and n type source region 16 and drain region 17 are formed.

Polysilicon/silicon junction field effect transistors and integrated circuits (POSFET)

Abstract: A junction field effect transistor is fabricated in crystalline silicon by using oppositely doped polysilicon as the gate (POSFET). The depletion region of the pn (or np) junction formed at the polysilicon/silicon interface is used as the gate electrode to modulate the current path through the silicon channel from source to drain, the source and drain contacts may either be conventional metal or polysilicon heavily doped of the same conductivity type as the single crystal silicon substrate.

Extrinsic infrared detector with a charge reset function

Abstract: A preferred embodiment of the invention is a three-gate charge-coupled device (CCD) which is designed to operate at cryogenic temperatures (circa 1-20° K). For an N channel device, a low-concentration N type material is separated from a P type substrate by a thin layer of intrinsic material. The active detection area is underneath a transparent detector gate which functions as the device's input gate. Electrons excited into the conduction band under the detector gate flow into the conduction band under the adjoining second gate which functions as an integrating gate by collecting the electrons that flow from under the input gate. The third gate also adjoins the second gate and is called the readout gate. When the readout gate is at a low potential, it dams up the electrons in the conduction band under the integrate gate. When the readout gate is at a potential at least as high as that of the integrate gate, the electrons may flow into a drain which adjoins the readout gate provided that the drain is at a potential higher than that of the readout gate; otherwise, electrons may flow from the drain into the conduction band underneath all three gates if the drain has the lowest potential of the four. Such a device may be constructed as a monolithic two-dimensional array with the drains extending in the Y-direction and the gates extending in the X-direction. Electrons lost by absorption of photons may thus be replaced.

A method of fabricating a MOS transistor on a substrate

Abstract: The invention relates to fabrication techniques for the construction of MOS transistors to provide source/drain regions (20,22) which are self-aligned and non-overlapping with respect to their gate electrode (16). The non-overlapping feature is provided by defining a gate electrode (16) over a substrate (10), forming an implant mask of dielectric (18), for example, on the sides of the gate electrode (16), and implanting a source/drain region (20,22) such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode (16) and the implanted regions (20,22). The source/drain region (20,22) is then heat driven until its side edge is substantially aligned with the edge of the gate electrode (16). Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.

The effect of thin gate dielectrics on scaling MOS devices

Abstract: T h i s p a p e r e x p l a i n s t h e o r i g i n a n d m a g n i t u d e o f c e r t a i n " t h i n d i e l e c t r i c e f f e c t s " a n d t h e i r i mp l i c a t i o n o n f u t u r e i n t e g r a t e d c i r c u i t d e s i g n . The f i r s t o f t h e s e e f f e c t s was p o i n t e d o u t i n R e f e r e n ces[1,2,3]and wil be c a l l e d t h e c h a n n e l c a p a c i t a n c e e f f e c t . It i s an e x t e n s i o n o f t h e n o n l i n e a r dependence o f channel charge on gate vo l tage above t h e c l a s s i c a l t h r e s h o l d v o l t a g e . T h i s n o n l i n e a r r e g i o n does n o t s c a l e w i t h a n y d e v i c e p a r a m e t e r and i s s t r o n g l y d e p e n d e n t o n t h e t h e r m a l v o l t a g e , KT/q. I n o r d e r t o o p e r a t e d e v i c e s a b o v e t h i s t r a n s i t i o n r e g i o n , a l o w e r limit on the power s u p p l y v o l t a g e i s s e t . The second t h i n d i e l e c t r i c e f f e c t i s t h a t t h e c h a n n e l c a r r i e r m o b i l i t y i s r e d u c e d w i t h i n c r e a s i n g s u r f a c e e l e c t r i c f i e l d . T h i s h a s b e e n e x p e r i m e n t a l l y v e r i f i e d b y Sun and Plummer. [4]