Showing papers on "MOSFET published in 1972"

Design of micron MOS switching devices

Abstract: Modern photolithographic technology offers the capability of fabricating MOSFET devices of micron dimensions and less. It is by no means obvious that such small devices can be designed with suitable electrical characteristics for LSI switchivg applications. In this talk we will describe short-channel devices ( L_{eff} \sim 1 µ) designed by scaling down larger devices with desirable electrical characteristics. Lateral and vertical dimensions, doping level, and operating voltages and currents are scaled in a self-consistent fashion. In this way small devices have been fabricated without the usual deleterious effects associated with short channels. The measured characteristics of these short-channel devices and the larger devices from which they were scaled will be compared.

Characteristics of p-channel MOS field effect transistors with ion-implanted channels

Abstract: Ion implantation technology was employed in the fabrication of MOS devices. Boron doses in the range of 0·4 × 10 12 to 1·72 × 10 12 ions/cm 2 were implanted into the channels of MOSFETs at 42 keV. Both low threshold enhancement-mode and depletion-mode devices were obtained. The variation of threshold voltage of enhancement-mode devices, and drain to source current of depletion-mode devices as a function of boron doses was reported. It was found that boron implantation under these conditions has no significant effect on the current gain constant k ′, P − N junction leakage current, or threshold stability of MOS devices. Boron implanted MOS capacitors were also studied. The C − V plots on capacitors implanted with moderate doses exhibit parallel shifts to the positive voltage direction, due to the presence of the very shallow non-uniformly doped layer on the silicon surface.

Dynamic mos ttl compatible

Abstract: The dynamic MOS TTL compatible input voltage level translator has an input terminal for receiving a TTL voltage level for transmission to the gate of a load MOSFET through a transmission gate MOSFET. The gate of the transmission gate MOSFET is connected to a switching bias circuit which turns on the transmission gate MOSFET to transmit the TTL input voltage, and turns off the MOSFET to maintain a voltage comprising the TTL voltage plus a bootstrap voltage at the gate of the load MOSFET. The bootstrap voltage is added through the use of an enhancement capacitor which is connected between the gate and the drain of the MOSFET load device, the drain also being connected to an input for receiving a clock complement signal. A switch MOSFET device has its gate connected through a terminal for receiving a clock signal and has its drain connected at a junction to the source of the load MOSFET device, the junction providing an output signal of a MOS amplitude voltage for application to succeeding MOS stages.

Dual voltage fet inverter circuit with two level biasing

Abstract: An inverter circuit utilizing transistors of the MOSFET type, for example, incorporates positive capacitive feedback and both high and low voltage power sources in a manner that results in an exceedingly low figure of merit (speed-power product). The highvoltage source is associated with an a-c grounded portion of the circuit and, in conjunction with a ''''kicker'''' type of capacitive voltage feedback, produces a relatively high overdriving gate-tosource voltage differential on a load transistor so as to effect rapid output signal transitions. The low-voltage source, connected to the load transistor, which forms a part of a selectively d-c grounded output portion of the circuit, allows the use of relatively small load and driver transistors so as to conserve chip space, minimize total circuit power dissipation, increase transistor yields and reduce manufacturing costs.

Self-heating and gate leakage current in a guarded MOSFET

Abstract: Gate leakage current measurements of a guarded MOSFET show that device self-heating has a marked effect on the Schottky emission current. This effect can make the bias conditions for zero gate leakage current very sensitive to changes in drain voltage.

Integrated circuit of the MOS variety

Abstract: A MOSFET read/write random access memory is disclosed in which the individual bit cells perform individually, autonomously but concurrently refresh operation upon application of write pulses. Information can be changed in an addressed cell in a write cycle, and copies from the cell in a read cycle. The cells each are constructed from three MOSFET''s, two nodes and a voltage gated or voltage dependent capacitor. The latter capacitor has just one main electrode and a gate of MOSFET-like configuration. The principle circuit involving that capacitor has the gate of a regulative MOSFET connected to the capacitor gate, both gates are or pertain to a node. A signal on the main electrode is transmitted by the capacitor only when the node is charged and only then is the regular MOSFET rendered conductive. The two other transistors and the additional node in a cell serves as charge transfer and addressing elements.

Mosfet memory cell

Abstract: A MOSFET memory cell system wherein a plurality of one transistor per bit cells is combined with a three transistor switching circuit.

A hybrid monostable delay circuit

Abstract: A hybrid monostable circuit employing a bipolar and a low threshold voltage MOSFET transistor is described. The configuration, which consumes zero standby power, is compatible with regular single-rail logic systems and can provide variable time delays in excess of 1-min duration.

Radiation effects on three low-power microcircuits

Abstract: Irradiation of several low power circuit elements by Co-60 gamma radiation, low and high energy electrons, and neutrons is discussed. The bipolar circuits were SE480 Q NAND gate, and a micropower frequency divider was used in electronic wrist watches. The MOS device was a dual p-channel MOSFET.