Showing papers on "Multiplexer published in 1975"

Distributed input/output controller system

Abstract: A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral-unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to carry both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral-unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series. Data may be transferred directly between a computer memory unit and the peripheral devices without requiring the use of any computer working registers and without requiring subroutines to preserve an ongoing main program. Each peripheral-device controller can issue interrupt signals which are processed by the computer on a priority basis when they occur simultaneously. Some microengines employ two sets of programmed microcodes and each set is selectable by a switch, such as a wire jumper, for controlling either of two different kinds of devices.

Communication multiplexer module

Abstract: A communications multiplexer module (CMM) assembles serial by bit data from a plurality of input ports into parallel-by-bit characters before transmitting them to a host computer. On output operations the host computer supplies characters parallel-by-bit to the communications multiplexer module and the module disassembles the characters into serial by bit data for distribution to output ports. The CMM includes a main memory for storing control words, there being one control word for each port. The main memory is scanned in a fixed sequence so that the control words are read out of the main memory in the same sequence that the input and output multiplexers for the ports are scanned. This permits most of the logic circuits of the CMM to be time shared between all ports the logic circuits being controlled in turn by each control word. Any port may be an input or an output port, the designation being determined by bits of the control word associated with the port. The control word also contains bits designating whether the port is to function in association with a synchronous or an asynchronous line adapter connected to the port, the number of bits in each character, and other information necessary for assembling input or disassembling output data and controlling the transfers between the ports and the computer. The control word has a character assembly/disassembly area where characters are assembled a bit at a time during input operations, and are disassembled a bit at a time during output operations. Characters are transferred between the assembly/disassembly area and the host computer through a storage area in the control word. Character detect tables are provided for sensing each input character after assembly, or each output character before disassembly and, if it is a control character, converting it into a standard control word code used within the CMM. The outputs from the character detect table control certain hard wired functions and, in addition, may address a second memory containing a plurality of control interpretation tables. In the character interpretation tables, each bit represents a specific function to be performed within the CMM. The control word associated with each port contains bits designating which character detect table and which control interpretation table is to be utilized with the port. This enables the CMM to recognize and respond to control functions in a uniform manner, even though the functions themselves may be represented by characters in different codes. Programmable procedure counters are provided for detecting various conditions such as a failure to detect an end character. Full error checking procedures are included in the CMM.

Method of transmitting information and multiplexing device for executing the method

Abstract: A method and a TDM multiplexer by which circuit-switched synchronous data and packet-switched asynchronous data are optimally combined for transmission over a common channel. Time slots of variable width are assigned to circuit-switched traffic, while the remaining capacity of the TDM frame is used for transmission of store-and-forward traffic which is inserted in the gaps between assigned time slots in the form of an intermittent bit stream.

Digital two-wire irrigation control system

Abstract: Apparatus for the control of a number of remotely located irrigation or sprinkler valves from a central location by means of control signals encoded onto a single pair of power transmission lines linking a central encoder and a number of remote decoders. The encoder includes a multiplexer for selecting on/off signals supplied by a controller, an address generator to drive the multiplexer and to generate decoder addresses for transmission, and coupling circuitry to encode the generated decoder addresses and on/off signals onto an alternating-current power signal, by clipping half-portions of the signal to represent zero values. Each decoder includes a bridge rectifier, from which clock pulses and a serial data stream are derived. The data stream is continually shifted through a shift register, and a comparator compares a decoder address field in the register with the conditions of a set of manual switches indicative of the decoder address. When the comparator finds a match, the on/off signal is gated into a flip-flop and utilized to generate a valve control signal.

Peripheral-unit controller apparatus

Abstract: A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral-unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to carry both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral-unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series. Data may be transferred directly between a computer memory unit and the peripheral devices without requiring the use of any computer working registers and without requiring subroutines to preserve an ongoing main program. Each peripheral-device controller can issue interrupt signals which are processed by the computer on a priority basis when they occur simultaneously. Some microengines employ two sets of programmed microcodes and each set is selectable by a switch, such as a wire jumper, for controlling either of two different kinds of devices.

Security alarm system

Abstract: A plurality of alarm conductors are coupled to a multiplexer which connects the conductors one at a time in sequence to the input of an alarm detector which detects alarm conditions on the conductors. A shift register having the same number of stages as the number of alarm conductors has its input coupled to the multiplexer output and its output coupled back to its input to form a recirculating serial memory. The shift register is clocked in synchronism with the multiplexer. The output of the shift register is selectively coupled through a switchable memory output control to the input of the alarm detector to recall a previous alarm condition on one or more of the alarm conductors. A second shift register having a number of stages equal to an integral multiple of the number of alarm conductors has its input coupled to the output of the alarm detector means. The second shift register is also clocked in synchronism with the multiplexer. An exclusive OR circuit has one input coupled to the output of the second shift register, another input coupled to the output of the alarm detector, and the output coupled to the control means for a data transmitter which transmits the alarm to a remote location. The second shift register and exclusive OR circuit limit the number of times the alarm is transmitted to the remote location.

Contiguous channel multiplexer

Abstract: An improved multiplexer especially adapted for combining a plurality of microwave signal channels for transmission over a common transmission path is disclosed. A single "directional filter" multiplexer structure is utilized to combine contiguous or adjacent channels without resort to odd-even channel separation or additional equalization and/or compensation networks. By purposely extending the bandpass characteristics of preselected channel filters so that either or both of their cutoff frequencies extend substantially past their associated channel band edges and well into the reflection loss regions of the adjacent channel or channels the adjacent channel mutual interaction effect is exploited. The resultant interaction between the transmission characteristics of one channel and the reflection characteristics of the adjacent channel yields an overall transmission characteristic for each channel which meets the multiplexer loss, loss slope and group delay requirements while minimizing the need for equalizing or compensating devices.

Automatic channel assignment circuit

Abstract: An automatic channel assignment circuit in a controlling association with an asynchronous or synchronous digital time division multiplexer and demultiplexer combination at one communication terminal to assign channels of transmitted and received synchronous data streams to asynchronous or synchronous source data signals in a manner to minimize temporary data memory regardless of the number of different bit rates of the source data signals by assigning the data signals to channels of the associated one of the transmitted and received data streams so that the bits of each of the data signals tend to have equal spacing throughout the bits of the associated one of the transmitted and received data streams. Each of the transmitted and received data streams have a predetermined fixed data format with respect to the channels and a given bit rate greater than the total of the bit rates of the source signals. However, the automatic channel assignment circuit provides, in effect, an automatically determined-at-the-time-of-rate-selection a variable data format with respect to the ports. The channel assignment control circuit also includes a means to automatically indicate when the total of the mixture of bit rates has exceeded an allowable maximum.

Programmable interface apparatus and method

Abstract: An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations. Each multiplexer unit includes a plurality of storage registers which are operatively coupled to the programmable interface associated therewith for receiving control information therefrom designating the priority to be given by the unit to the processing of different types of interrupt signals received from devices associated therewith in addition to information designating which one of a set of processing routines to be used in servicing the interrupt.

Digital signal generator

Abstract: Digital signal generator for producing digital signalling codes employed in a digital telephone communication system including several tone generators for providing presynthesized digital tone signals which are convertible to audible tones. Permutable digital codewords are produced by a codeword generator. Some of the tone signals and codewords are combined by FSK and switching circuitry. Tone signals, codeword signals, and combination signals are stored in storage registers and read out by a multiplexer to provide a continuous TDM bit stream of 60 channels of digital signalling codes.

Method and apparatus for path testing in a time division multiplex switching network

Abstract: After marker functions have been performed to set up a network path during normal call processing, a continuity word is inserted into the path. The output of the path is coupled back to the input via a test multiplexer at the input to circulate the continuity word. A word is taken from the path being tested after circulation and is compared to the original continuity word, with identity of comparison being verification of continuity. Continuity test apparatus includes a continuity word register and a comparator. The comparator has inputs from the continuity word register and from the network output for the path being tested. The continuity word may be inserted in the path from an output access memory for maintenance and test words, having its output to the same multiplex lead as the output buffer memory. The continuity word may also be taken from the continuity word register, and from there supplied to a third input of the test multiplexer, and this input is enabled during the time slot of one frame to insert the continuity word. If the network includes access from a controller to input and output buffer memories, the continuity test apparatus may be omitted, and direct reading and writing of the buffer memories used to insert and extract the continuity word from the path being tested, and the comparison is then done in the controller. The test path may also be extended via TDM digital lines to a remote line switch, where the outgoing channel is coupled back to the incoming channel in response to continuity test commands.

Input/output multiplexer security system

Abstract: An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command signals and at least one multiplexer unit which directly controls transfers between the memory module and any one of a plurality of peripheral devices coupled to different ports of the multiplexer unit. The system interface unit operatively provides connections between different ones of the modules during the execution of commands included within user programs. The multiplexer unit includes sets of registers selectable under program control which store information which enables user programs for accessing the memory module. Additionally, other ones of these registers store control information used to control the processing of interrupts as well as other operations independently of user programs. The multiplexer unit includes apparatus which operatively couples these registers and is responsive to commands to ensure that only authorized acceses to these registers are made during system operation. The system also provides access rights to those registers to different types of system software such that only the system routines having the appropriate privileges are able to transfer information to those registers within the multiplexer unit.

Direct indicator device for determining the cardiac output flow rate according to the thermodilution method

Abstract: A direct indicator device for determining the cardiac output according to the thermodilution method embodying two temperature sensors connected to the blood circulation for respectively determining the inlet- and dilution temperatures. A clock generator and a scaler connected at the output of the clock generator are provided, the scaler forming a control signal. A respective one of the sensors is connected in circuit with inputs of an associated temperature-pulse frequency converter, the outputs of which are connected with a respective input of a multiplexer. A control input of the multiplexer connected with the output of the scaler serves for the alternate switching-through of a signal from one input and from the other input of the multiplexer to the output thereof in time-dependent function of the control signal. A gate circuit has one input connected with the output of the multiplexer, another input connected with the output of the clock generator and a further input connected with the output of the scaler. The gate circuit has an output at which there appears the clock rate of the clock generator as a function of time on the one hand of the control signal and on the other hand of the signal at the output of the multiplexer, the output of the gate circuit being connected with the input of a counter. The output of the counter is connected with the input of an intermediate storage, and a control input of the counter and a control input of the intermediate storage are connected at the output of the scaler for the summation of the clock repetition rate delivered to the counter and for the storage thereof as a function of time of the control signal. A digital computer has connected therewith a digital indicator device, the computer having inputs connected respectively with the output of the intermediate storage, the output of the clock generator and the output of the scaler.

Steering code generating apparatus for use in an input/output processing system

Abstract: An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command sequences and a multiplexer unit which directly controls transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. The system interface unit which operatively provides connections between the different modules includes apparatus for generating steering codes defining the physical location of each module requiring service by another module of the system. The system interface unit appends information provided by the particular module generating a requesting request for attention to the steering code generated. The generation of steering code information by the system interface unit and the module included in such requests insures that only authorized accesses are made to the different modules during the input/output processing unit's execution of programs during the running of processes associated therewith.

Digital firing pulse generator for thyristor power converters

Abstract: A digital pulse generator for firing thyristors in a polyphase converter system is described in an hybrid analog-digital and in an all digital form. A phase locked oscillator associated with a digital counter generates timing waveforms synchronized with the phase lines to establish firing angles in relation to a reference signal. Each firing pulse triggers the logic circuit of a distributor and a multiplexer is coupled with such logic circuitry in order to insure that the proper timing waveform is selected so as to match the selection of the next thyristor to be fired.

Multiplexer transmitter terminator

Abstract: A multiplexer transmitter terminator is disclosed for connection to a multiplexer transmitter in a system having a plurality of multiplexer transmitters connected on a common communication line. Each of the multiplexer transmitters is assigned a time period for transmission relative to a multiplexer time clock. The improvement includes a counter circuit connected to the multiplexer time clock for providing a counter output upon counting a preselected number of clock pulses which output corresponds to the time period assigned for transmission of the multiplexer transmitter. A line receiver is connected to the communication line for providing an output upon detecting a predetermined period of signal absence on the communication line. The line receiver output is connected to the counter circuit to reset the counter after the predetermined period of signal absence. The counter circuit is connected to the multiplexer transmitter for enabling transmission through the communication line only at the time period assigned to the multiplexer transmitter. The foregoing abstract is merely a resume of one general application, is not a complete discussion of all principles of operation or applications, and is not to be construed as a limitation on the scope of the claimed subject matter.

Multiplexer receiver terminator

Abstract: A multiplexer receiver terminator is disclosed for connection to a multiplexer receiver in a system having a plurality of multiplexer receivers connected on a common communication line. Each of the multiplexer receivers is assigned a time period for reception relative to a multiplexer time clock. The improvement includes a counter circuit connected to the multiplexer time clock for providing a counter output upon the clock counter counting between two preselected clock counts which correspond to the time period assigned for reception of the multiplexer receiver. A line receiver is connected to the communication line for providing an output upon detecting a predetermined period of signal absence on the communication line. The line receiver output is connected to the counter for resetting the counter after the predetermined period of signal absence. The counter circuit is connected to the multiplexer receiver for enabling reception from the communication line only during an output of the counter circuit. The foregoing abstract is merely a resume of one general application, is not a complete discussion of all principles of operation or applications, and is not to be construed as a limitation on the scope of the claimed subject matter.

System for digitizing and interfacing analog data for a digital computer

Abstract: A system for digitizing and interfacing analog data from a plurality of amplitude modulated periodic signals with a computer in which an alternating reference signal is identified and sampled input data to be digitized is synchronized at the same time reference point of the waveform of the reference signal. Pulses from a real time clock are counted and synchronized with the reference signal and this synchronized signal is delayed and fed to a timing circuit which starts the multiplexing of the input signals and also activates an address counter to initialize the address locations in the computer. The analog data from the multiplexer is converted to digital values by an analog-to-digital converter and fed to the computer at the given address.

Data transfer system

Abstract: A business machine for communicating with remote and/or local data devices. A multiplexer selects the device to communicate with the business machine and sequences the operation of the machine through its several steps under control of a central processing unit. Those data devices with which the business machine communicates on a party line are coupled to the multiplexer through a communications controller which detects Attention signals, requests access to the memory, and in response to acknowledgement of access, transfers characters between the data device and the memory. The controller receives a block check character but generates a modified block check character which simplifies the utilization of that check. A video display can be provided with the business machine. The business machine is organized to permit clearing of the display screen independently of clearing of the corresponding memory locations and to permit rapid scrolling of text on the display screen, even when a relatively low speed microprocessor is utilized for the central processing unit.

Apparatus for recording in a digital form signals detected during magneto-telluric prospection

Abstract: A recording apparatus for recording digital signals corresponding to components of telluric and magnetic fields. The apparatus comprises an analog input stage, a low pass filter stage, an analog output stage, an analog multiplexer and an analog-to-digital converter and recording system for recording the digital signals. A gain computing module is provided as well as a recording selector to achieve variable amplification gains in the analog input and output stages as well as variable frequency bands in the low pass filtering stage to accommodate different frequency input signals for low frequency recording, intermediate frequency recording and high frequency recording.

A JFET/bipolar eight-channel analog multiplexer

Abstract: Describes the design and fabrication of the first of a new generation of analog multiplexers using the bipolar/ionimplanted JFET process. The switch configuration used is especially suited to this process, and consequently results in a moderate size bipolar IC. The design of the switch, aided by the process characteristics, produces a high-performance monolithic multiplexer which can withstand input signals of greater than the power supplies and does not require special care in handling. A high degree of optimization is attained in the design of the bias circuits, and this plays a major role in achieving high fabrication yield, and subsequently low production costs.

Method for the time division multiplex transmission of data

Abstract: A method for transmitting data according to time division multiplex principles is described. In each multiplex frame synchronizing bits and data bits are transmitted from a multiplexer at the transmitter over a transmission device to a multiplexer at the receiver. In each time division multiplex frame a constant number of data bits are transmitted. The synchronism of the transmitter and receiver multiplexing devices and the transmission devices located at the transmitter and receiver are established by altering the duration of the time division multiplex frame.

Laser velocimeter real time digital data analyzer

Abstract: A digital analyzer for a laser velocimeter which compresses data into groups for a histogram display. A data processor containing the velocimeter information is fed through a multiplexer to a memory which is controlled by a data interrupt circuit that is fed by a two-phase clock. One phase of the clock pulses an address counter which feeds the multiplexer and a first digital-to-analog converter that controls the x-drive of a cathode ray tube. The data processor also has an output fed to a full adder and then fed back to the memory with the same output being fed to a storage register followed by a second digital-to-analog converter that controls the y-drive of the cathode ray tube.

Equipment self-repair by adaptive multifunction modules

Abstract: An equipment self repair apparatus utilizing the substitution of redundant circuits for a failure in any original operating logic module The substitution is accomplished through the use of a multiplexer unit which disconnects the faulty circuit and switches a built-in spare in its place

Electronic musical instrument employing digital multiplexed signals

Abstract: An electronic musical instrument, such as an organ, includes a multiplexing system for simultaneously scanning key switches on all of the manual keyboards and pedalboards sequentially an octave at a time and further for simultaneously and sequentially scanning all coupler controls to produce a digital output signal having pre-assigned positions for each of the different notes represented by operation of a coupler switch or a key switch in all of the coupler control sections and the keyboard sections of the organ. This digital signal is supplied to de-multiplexer keyer circuits for reproducing sound signals supplied to the output loudspeakers of the organ. The digital signal is sampled simultaneously in de-multiplexer/keyer circuits (for flute, chiff, celeste, swell string, great string) once each cycle thereof by a strobe pulse which is displayed by differing amounts prior to its application to different ones of the keyers to compensate for the different numbers and range of tones reproduced by the keyer circuits. This is done to correlate and align the tones reproduced by the different keyer circuits for producing the composite of tones supplied to the loudspeakers.

Digital signal multiplexer/concentrator

Abstract: A synchronous time division multiplex (STDM) system for sampling 1 through N digital input data signals from their respective 1 through N input channels at their respective frequencies F 1 through F N for concentration and retransmission over a single output channel at a frequency F 0 >Σ F n is disclosed. The data bit stream of each input channel is alternately coupled to first and second similar sections, A and B, of each input-channel-associated concentrator at fixed successive sample times T S . While the input data bits are coupled to and stored in the first section A during the sample time 1T S , the input data bits previously coupled to and stored in the second section B during the immediately previous sample time OT S are being retransmitted in their concentrated form on the output channel. On the next successive sample time 2T S the input data bits are coupled to and stored in the second section B while the input data bits previously coupled to and stored in the first section A during the immediately previous sample time 1T S are being retransmitted in their concentrated form on the output channel. This alternate sample, concentrate and then retransmit operation continues at successive sample times T S .

Digital data system: Digital multiplexers

Abstract: The two-stage multiplexing hierarchy developed for the Digital Data System is described. Included in this hierarchy are three synchronous time-division multiplexers and a new 64-kb/s cross-connect arrangement that offer both flexibility and simplified administrative procedures. Maintenance for the multiplexers is provided on an in-service monitoring basis and includes automatic switching of a “hot” spare in the event a fault is detected.

Chopping correlator for a MSK data signal

Abstract: The MSK signal is distributed to eight choppers, each of which also has coupled thereto a different sum or difference cosine or sum or difference sine chopping signal. The output signals from the choppers are summed in selected pairs in summers whose output signals are integrated over a predetermined number of unit time intervals. Coupled between four of the summers and four of the associated integrators there is an integrated time selector which enables adjusting the integrator output for different baud rates of the MSK signal input. The output signals of the integrators are coupled in pairs of multiplexers whose output signals in turn are coupled to sample and hold circuits. The output signals of the sample and hold circuits are coupled to another multiplexer whose output signal is coupled to an analog-to-digital converter to provide the data carried by the MSK signal in digital form. The correlator will provide an output from the analog-to-digital converter at a steady rate of two correlation coefficient values per unit interval for a given baud rate.

System for digitally converting baseband channel signals into a frequency-division multiplex signal and vice versa

Abstract: System for digitally converting baseband channel signals into a frequency-division multiplex signal. The system comprises at its input converter circuits by each of which the sequence of codewords of the digital signal which correspond to each signal to be converted is divided into two interlaced sequences. The two devices required for processing each of the two digital signals supplied by the input circuits in the form of converters are combined so as to use in cascade a Fourier transformation device, a set of arithmetic units in the form of digital filters and a time-division multiplexer which supplies the desired multiplex signal. Use: multiplex transmission of speech signals.

Asynchronous, multiplexing, single line transmission and recovery data system

Abstract: Asynchronously multiplexed sample data sub-systems employ transmission over a single line to a remote synchronizer and demultiplexer. At the remote synchronizer, the data is recovered by synchronizing signals derived from the data itself. A sub-system, or satellite location, supplies continuously sampled binary data along with a satellite identification and synchronizing sequence as a satellite message frame. This information is supplied bit-serially, to a multiplexer junction. The multiplexed satellite information is delivered asynchronously onto a single line transmission channel with other like bit serial satellite message information from other satellite monitoring sites. Such satellite information is transmitted to a central collection and analysis site where it is demultiplexed according to the words and bits that make up a satellite message frame. At least two message frames from each satellite monitoring site are always placed on the single transmission channel as a single block of data for that satellite. This technique, at the demultiplexer, assures proper recognition of a desired message frame based upon a comparison of satellite identification sequences and a frame synchronization sequence.