Showing papers in "IEEE Journal of Solid-state Circuits in 1975"
TL;DR: In this article, a load network is synthesized to have a transient response which maximizes power efficiency even if the active device switching times are substantial fractions of the a.c. cycle.
Abstract: The new class of amplifiers described is based on a load network synthesized to have a transient response which maximizes power efficiency even if the active device switching times are substantial fractions of the a.c. cycle. The new class of amplifiers, named `Class E,' is defined and is illustrated by a detailed description and a set of design equations for one simple member of the class. For that circuit the authors measured 96 percent transistor efficiency at 3.9 MHz at 26-W output from a pair of Motorola 2N3735 TO-5 transistors. Advantages of Class E are unusually high efficiency, a priori designability, large reduction in second-breakdown stress, low sensitivity to active-device characteristics, and potential for high-efficiency operation at higher frequencies than previously published Class-D circuits.
1,902Â citations
TL;DR: This second paper describes a two-capacitor successive approximation technique which, in contrast to the first, requires considerably less die area, is inherently monotonic in the presence of capacitor ratio errors, and which operates at somewhat lower conversion rate.
Abstract: For pt.I see ibid., vol.SC-10, no.6, p.371-9 (1975). Describes techniques for performing A/D conversion compatibly with standard single-channel MOS technology. This second paper describes a two-capacitor successive approximation technique which, in contrast to the first, requires considerably less die area, is inherently monotonic in the presence of capacitor ratio errors, and which operates at somewhat lower conversion rate. Factors affecting accuracy and conversion rate are considered analytically. Experimental results from a monolithic prototype are presented; a resolution of eight bits was achieved with an A/D conversion time of 100 /spl mu/s. Used as a D/A convertor, a settling time of 12.5 /spl mu/s was achieved. The estimated total die size for a completely monolithic version including logic is 5000 mil/SUP 2/.
772Â citations
TL;DR: An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area which allows a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.
Abstract: An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data is also presented which allows a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.
169Â citations
IBM1
TL;DR: In this article, the authors proposed a composite model to the monolithic IC yield problem, which is a multiparameter fit to a set of data originally described by Moore (1970), and showed that these same data can be modeled equally well with negative binomial statistics with two parameters.
Abstract: In a recent paper, see ibid., vol. Sc-9, no.3, p.86-95 (1974), Warner proposed a composite model to the monolithic IC yield problem. This composite model is a multiparameter fit to a set of data originally described by Moore (1970). It is shown that these same data can be modeled equally well with negative binomial statistics with two parameters.
131Â citations
IBM1
TL;DR: New concepts are introduced relating aspects of circuit theory to the multicapacitances which can be obtained from a computer program for multiconductor geometries which are applied to the wiring of an integrated circuit chip.
Abstract: New concepts are introduced relating aspects of circuit theory to the multicapacitances which can be obtained from a computer program for multiconductor geometries. These concepts are applied to the wiring of an integrated circuit chip. Capacitances are found for crossovers, vias, and right angle bends for a realistic geometry.
104Â citations
IBM1
TL;DR: A model of the effect of random fluctuations in the number of impurity atoms in the depletion layer of a field-effect transistor (FET) is presented and analyzed and the range of space charge per unit area that must be anticipated on a chip containing N FET's each of area A is conducted.
Abstract: A model of the effect of random fluctuations in the number of impurity atoms in the depletion layer of a field-effect transistor (FET) is presented and analyzed. It is conducted that the range of space charge per unit area that must be anticipated on a chip containing N FET's each of area A is /spl Delta/S=q(2 ln N)/SUP 1/2/A/SUP -1/4/n~/SUP 1/2/. n~ is the doping level of the substrate.
102Â citations
TL;DR: Close-form expressions for intermodulation distortion produced by variable-capacitance diodes in series- and parallel-tuned circuits are derived and verified by experiment at frequencies up to 200 MHz.
Abstract: Distortion in variable-capacitance diodes is analyzed using the Volterra series approach. Closed-form expressions for intermodulation distortion produced by variable-capacitance diodes in series- and parallel-tuned circuits are derived and verified by experiment at frequencies up to 200 MHz. The choice of the diode capacitance law exponent for minimum distortion is investigated. Distortion in multiple-diode connections is analyzed and the advantages of the back-to-back connection is shown. Calculation shows the elimination of third-order distortion for n=0.5 in this connection.
101Â citations
TL;DR: The selection of the optimization criterion is discussed and an interesting approach to improving the performance of MOS off-chip drivers has previously been described.
Abstract: An interesting approach to improving the performance of MOS off-chip drivers has previously been described (see ibid., vol.10, no.2, p.106 (Apr. 1975)). The selection of the optimization criterion is discussed.
95Â citations
TL;DR: In this article, the potential equilibration method was used for CCDs with any number of phases and it was shown that, if the active gate areas are suitably enlarged, harmonic distortions of less than -60 dB may be expected.
Abstract: This has been studied by measuring the generated higher harmonic components of a sinusoidal input. Results obtained with various injection methods and device geometries have been compared. Best results, with all harmonic components more than 40 dB below the fundamental, have been obtained for surface channel devices with a potential equilibration method in which the signal is applied to a second input gate, while the first input gate is held at a d.c. reference potential. It is concluded that this version of the potential equilibration method is readily adoptable for CCDs with any number of phases and that, if the active gate areas are suitably enlarged, harmonic distortions of less than -60 dB may be expected.
65Â citations
TL;DR: An experimental and theoretical study of double-diffused MOS transistors (DMOST's) has been made in this paper, where a simple analytic two-transistor model gives insight into DMOS device physics as well as predicting DMOST characteristics.
Abstract: An experimental and theoretical study of double-diffused MOS transistors (DMOST's) has been made. A simple, analytic two-transistor model gives insight into DMOS device physics as well as predicting DMOST characteristics. Both the model and experimental results show that three distinct regions of operation exist: short-channel control, long-channel control, and carrier velocity saturation control. Quantitative criteria are established for judging the region of operation as a function of device parameters and terminal voltages. A DMOST may be optimized to have the same d.c. characteristics as its short-channel component transistor over most of its operating range. A two-transistor model suitable for Computer-Aided Circuit Design (CAD) is also presented.
60Â citations
TL;DR: The results show that ultra high speed random access NDRO memories with zero standby power can be built with Josephson devices.
Abstract: The design and experimental investigation of a Josephson tunneling memory cell with nondestructive readout (NDRO) is described. The cell consists of a relatively large (20/spl times/25 mil/SUP 2/) superconductive loop which contains two Josephson tunneling write gates. NDRO is performed with a third gate per cell. It is shown that such a cell is an L, R, C parallel circuit which must be critically damped. Design equations are established which ensure critical damping solely with the single-particle tunneling resistance of the gates. Current transfer time (cell switching time) was measured to be /spl sime/600 ps. From two consecutive write cycles it was estimated that writing could be performed with a repetition rate of /spl ges/1 GHz. No loss in circulating current was detected after 5/spl times/10/SUP 8/ NDRO cycles. The operating margins, measured without word, bit, and sense disturbs, allowed independent variations of /spl plusmn/11.5 percent in word current, /spl plusmn/26 percent in bit current, and /spl plusmn/15 percent in sense current. These results show that ultra high speed random access NDRO memories with zero standby power can be built with Josephson devices. Smaller switching times are expected in miniaturized memory cells.
[...]
TL;DR: In this paper, a novel form of integrated injection logic (I/SUP 2/L) is described, in which the device structure has been designed specifically for high packing density and low power-delay product.
Abstract: A novel form of integrated injection logic (I/SUP 2/L) is described, in which the device structure has been designed specifically for high packing density and low power-delay product. The basic logic element is a multi-input, multi-output gate, formed in a single-base land by using several diffused collectors and several Schottky base contacts. The lateral p-n-p injector of conventional I/SUP 2/L has been replaced by a vertical arrangement. Factors affecting packing density and power-delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. A preliminary process to demonstrate the feasibility of the vertical injector is described and the measured transistor parameters and power-delay product are given. Experiments to determine suitable conditions for the formation of Schottky barrier diodes are presented, and satisfactory performance for the complete process is demonstrated.
TL;DR: A new type of negative-resistance device utilizing a simple combination of complementary JFET's, which is suitable not only for discrete use but for use as a unit cell in bipolar integrated circuits (IC's) is proposed.
Abstract: A new type of negative-resistance device utilizing a simple combination of complementary JFET's, which is suitable not only for discrete use but for use as a unit cell in bipolar integrated circuits (IC's) is proposed. The basic structure and the essential fabrication technology are described, and varieties of unitary negative-resistance devices using the integrated complementary JFET structure are proposed. The principle of operation is discussed with numerical and experimental analysis. Empirical formulas for practical design have been established with satisfactory agreements with experimental results.
TL;DR: The use of input stage transconductance reduction as a means of decreasing monolithic op amp die size and increasing slew rate and compared to earlier techniques is discussed.
Abstract: The use of input stage transconductance reduction as a means of decreasing monolithic op amp die size and increasing slew rate is discussed. A new input stage circuit which provides improved slew rate is presented and compared to earlier techniques.
TL;DR: This paper describes some of the key peripheral circuits used in a practical 4K random-access memory (RAM) design paying particular attention to sense amplifiers and other on-chip circuits peripheral to the memory array.
Abstract: The use of a single transistor and storage capacitor allows MOS dynamic memories to be built with cell areas of less than two square mils. The logic signals then available are unusually small and balanced sensing is commonly used. Such sense amplifiers and other on-chip circuits peripheral to the memory array are increasingly important in determining the total area and cost, the performance and testing difficulties. This paper describes some of the key peripheral circuits used in a practical 4K random-access memory (RAM) design paying particular attention to these factors. A `margin test' facility is designed into the form of sense amplifier used and allows measurement of cell storage levels and sense amplifier offset to ensure that adequate signal margins exist in the memory.
TL;DR: In this article, the authors describe a new voltage-to-current converter that combines accuracy with differential signal handling and a high common-mode rejection ratio (CMRR) for an instrumentation amplifier consisting of two V2C converters in a balancing circuit.
Abstract: Describes a new voltage-to-current converter. This converter combines accuracy with differential signal handling and a high common-mode rejection ratio (CMRR). An application in an instrumentation amplifier consisting of two voltage-to-current converters in a balancing circuit shows the versatility of these units in analog circuit design. A remarkable point of the instrumentation amplifier is that the bandwidth (800 kHz) remains constant although the voltage gain varies from 1 to 10/SUP 4/.
TL;DR: A novel low-power low-component count CMOS charge-redistribution digital-to-analog (D/A) demultiplexer which produces a high resolution neuro-compatible charge output and an extended missing pulse code is developed which assures higher reliability and protection against excess and erroneous stimulations.
Abstract: Describes an implantable multielectrode neural stimulator developed for electrical stimulation of the auditory nerves with the aim of producing a sensation of sound in sensory deaf ears. Power and digitally coded amplitude and frequency data are transcutaneously transmitted to the implantable stimulator using an inductively coupled RF link and an ultrasonic link, respectively. A novel low-power low-component count CMOS charge-redistribution digital-to-analog (D/A) demultiplexer which produces a high resolution neuro-compatible charge output is described. An extended missing pulse code is developed which assures higher reliability and protection against excess and erroneous stimulations. An experimental 4-electrode system capable of stimulating up to a 5-kHz rate and consuming less than 10 mW of power is presented.
TL;DR: General expressions of the limiting and excess noise currents generated by a current mirror sink/source are derived and the noise characteristics of other current source topologies are compared and shown to be quite similar to the basic current mirror.
Abstract: General expressions of the limiting and excess noise currents generated by a current mirror sink/source are derived. The analysis, restricted to low and audio frequencies, shows the effect of the transistor base resistance and the noise reduction due to the external emitter degeneration. By means of a computer-aided design (CAD) analysis, spectral density frequency plots are computed, and the total noise content in the audio band calculated for the case of a typical 1/f excess noise generator. The noise characteristics of other current source topologies are compared and shown to be quite similar to the basic current mirror. Noise measurements of current mirrors implemented with IC transistor pairs showed a good correlation with the previous analytical and CAD results.
[...]
TL;DR: The experimental results demonstrate a factor of 2 improvement in power-delay efficiency of Schottky I/ SUP 2/L over conventional I/SUP 2-L.
Abstract: Schottky I/SUP 2/L uses the principles of integrated injection logic (I/SUP 2/L/MTL) and the properties of ion implantation to obtain improved performance at the same densities as conventional I/SUP 2/L. Schottky diodes are formed in the multicollectors of the switching transistor and reduce the signal swing, thus improving the power delay efficiency. An increase in the intrinsic speed limit is also feasible. The Schottky I/SUP 2/L structure and characteristics are described and contrasted with conventional I/SUP 2/L. A model which is useful for its design is discussed. Integrated test structures which provide direct comparison between conventional and Schottky I/SUP 2/L performance have been fabricated. The experimental results demonstrate a factor of 2 improvement in power-delay efficiency of Schottky I/SUP 2/L over conventional I/SUP 2/L.
TL;DR: In this paper, three different methods of domain control are presented: a separate Schottky barrier diode, a separate MESFET, and a barrier gate on the channel of the Gunn device.
Abstract: Monolithic integration of planar Gunn devices on GaAs is a very promising method to realize microcircuits for the Gbit/s range. Semiinsulating GaAs is readily available as substrate material. In this paper estimates of characteristic parameters of these circuits, such as maximum pulse rate, power consumption, and package density, are presented. Three different methods of domain control are available: a) by separate Schottky barrier diode; b) by MESFET; or c) by Schottky barrier gate on the channel of the Gunn device. Theoretical limits for these methods are given. Maximum pulse rates of 11, 5, and 7 Gbit/s, respectively, can be expected. Unidirectionality and trigger drive of the three methods are rated. Experimental integrated circuits were built to demonstrate the capability of the methods of domain control. Comparison with calculations yields good agreement. Coming close to the theoretical limits has not yet been accomplished in all practical cases since further miniaturization of the circuits and improvement of the material properties relevant to domain processes is needed. After progress in these two points it is expected that the theoretical limits will be reached.
TL;DR: A nonvolatile charge-addressed memory (NOVCAM) cell is described in a 64-bit shift register configuration and the charge address is performed by a charge-coupled device (CCD) shift register and the information is stored in metal-nitride-oxide-silicon (MNOS)nonvolatile sites located in parallel with the CCD shift register.
Abstract: A nonvolatile charge-addressed memory (NOVCAM) cell is described in a 64-bit shift register configuration. The charge address is performed by a charge-coupled device (CCD) shift register and the information is stored in metal-nitride-oxide-silicon (MNOS) nonvolatile sites located in parallel with the CCD shift register. The tunneling electric field strength across the thin-oxide MNOS structure is controlled by the magnitude of the charge transferred from the CCD register. The write, erase, and read modes of operation are discussed with typical /spl plusmn/20 V 10 /spl mu/s write/erase, and 2 V 2 /spl mu/s read conditions. Readout is accomplished by parallel stabilized charge injection from a diffused p/n junction to minimize access time to the first bit.
TL;DR: Experimental studies of connections formed in MOS-type structures by nanosecond dye laser pulses are described and a model for the connection process is presented which correlates well with the various observations and experiments.
Abstract: Experimental studies of connections formed in MOS-type structures by nanosecond dye laser pulses are described. Of particular importance are results relating to the reliability and reproducibility of the connection process. A model for the connection process is presented which correlates well with the various observations and experiments.
TL;DR: This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates, fabricated using a 25-/spl mu/m minimum linewidth technology.
Abstract: This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates. The algorithm adopted was that of a simple serial 4-bit multiplier consisting of a 4-bit adder with ripple carry, together with a four phase, 8-bit accumulator shift register. The circuit, fabricated using a 25-/spl mu/m minimum linewidth technology, operated with a minimum cycle time of 6.67 ns (a limit imposed by the external test equipment) giving a 4-bit multiplication time of 27 ns with an average power dissipation of 35 /spl mu/W per logic gate. With better external pulse generators, or internal Josephson junction generators, the present circuit has been simulated to operate with a 3.0-ns cycle giving a 4-bit multiplication time of 12 ns.
TL;DR: A two- quadrant and a four-quadrant multiplier are described for performing accurate multiplication of analog signals using devices of special geometry but capable of fabrication with a standard bipolar process.
Abstract: Describes a new method using emitter current crowding for performing accurate multiplication of analog signals using devices of special geometry but capable of fabrication with a standard bipolar process. A narrow region of current injection-a carrier domain-can be positioned on an emitter by one electrical input and controlled in magnitude by a second input. The resistive epi layer resolves this current into a differential output proportional to the product of the inputs. A key advantage of these multipliers is their low noise. The basic principle can be applied to many other nonlinear operations. A two-quadrant and a four-quadrant multiplier are described.
TL;DR: The maximum switching speed of FET logic elements has been evaluated for self-aligned structures with various channel lengths and various degrees of substrate decoupling via device-to-substrate capacitances.
Abstract: Extensive use has been made of the advantages ion implantation has to offer over standard processing for the fabrication of high performance n-channel MOS circuits. By combining an enhancement driver with a depletion load, the maximum switching speed of FET logic elements has been evaluated for self-aligned structures with various channel lengths and various degrees of substrate decoupling via device-to-substrate capacitances. An 11-stage ring-oscillator circuit is used for performance evaluation. Switching delays as small as 115 ps were obtained for such inverter stages built on 200 /spl Omega//spl times/cm substrate material and having 1-/spl mu/m channel length. Essential fabrication details and circuit behaviors are described.
TL;DR: Intended as an encoding component for high-speed parallel A/D converters, this `3-bit quantizer' uses regeneration for voltage gain and signal storage and a Gray-code output minimizes the problem of comparator indecision.
Abstract: Describes a monolithic circuit consisting of an array of 8 voltage comparators, a resistive voltage divider, and associated logic circuits. Intended as an encoding component for high-speed parallel A/D converters, this `3-bit quantizer' uses regeneration for voltage gain and signal storage. A Gray-code output minimizes the problem of comparator indecision. The principal error sources are an asymmetry-induced comparator offset with 2-mV standard deviation and a thermally induced offset of a much as /spl plusmn/2.5 mV, dependent on signal history. The quantizer has been incorporated in an experimental 6-bit 200 megasample/s (MS/s) A/D converter.
TL;DR: A programmable logic array (PLA) with J-K flip-flops as feedback loops and having a maximum operating speed of 12 MHz has been designed and realized in epitaxial-silicon-films- on-insulators (ESFI) silicon-on-sapphire (SOS) technology.
Abstract: A programmable logic array (PLA) with J-K flip-flops as feedback loops and having a maximum operating speed of 12 MHz has been designed and realized in epitaxial-silicon-films-on-insulators (ESFI) silicon-on-sapphire (SOS) technology. The advantages of the ESFI SOS technology and the circuit of the PLA are described and experimental results are presented. In addition, a twin PLA using metal-nitride-oxide-semiconductor (MNOS) transistors in the AND and OR matrices and having the same number of inputs, outputs, and feedback loops as the mask-programmable PLA has been designed. This MNOS PLA has full on-chip decoding capability and can be programmed or reprogrammed individually. The circuit of the MNOS PLA is described and the speed of the device is calculated.
TL;DR: The voltage-to-current converter is a versatile building block that can be applied as an instrumentation amplifier, a universal current mirror or current follower, etc.
Abstract: Presents a monolithic integrated differential voltage-to-current converter. The transconductance of the converter is determined accurately by one external resistor. A total error in the conversion factor as low as /spl plusmn/0.5 percent is obtained by using composite transistors and by using the mutual equality of integrated resistors. The transconductance has a nonlinearity of 0.02 percent and a temperature coefficient of 4/spl times/10/SUP -5///spl deg/C. The output impedance is 5 M/spl Omega/. The voltage-to-current converter is a versatile building block. It can be applied as an instrumentation amplifier, a universal current mirror or current follower, etc.
TL;DR: A 24-bit serial-parallel multiplier was integrated in CMOS/silicon-on-sapphire (SOS) technology on a 155 mil/spl times/170 mil chip and the operation of this multiplier is described, showing how the parallel loaded multiplier x combines with the serial loaded multiplicand a to form the serial product.
Abstract: A 24-bit serial-parallel multiplier was integrated in CMOS/silicon-on-sapphire (SOS) technology on a 155 mil/spl times/170 mil chip. The operation of this multiplier is described, showing how the parallel loaded multiplier x combines with the serial loaded multiplicand, a, to form the serial product. An addend, b, can also be accommodated to produce ax+b. The design of the multiplier cells are based on functional majority logic adders and weak or trickle inverter master-slave latches. The chip operates at clock rates up to 18 MHz. Power dissipation at 10 MHz and V/SUB DD/ of 5 V is about 20 mW, and the energy consumption for multiplying two 16-bit numbers is about 64 nJ. Typical application areas are mentioned.
TL;DR: A switched capacitor, p-channel, 1024 bit random access memory has been made with electron lithography with modest shrinking of feature size and the minimum access time of the memory was reduced from 100 ns to less than 50 ns.
Abstract: A switched capacitor, p-channel, 1024 bit random access memory has been made with electron lithography. The basic circuit was the same as that described by Boll and Lynch (see abstr. B35355 or C22818 fo 1973) but with halved lateral dimensions. The gate length of the switching transistor was 4 /spl mu/m, and the chip size was 1.2/spl times/1.8 mm. In order to fabricate the device, a 1 /spl mu/m alignment accuracy was required. Even with this modest shrinking of feature size, the minimum access time of the memory was reduced from 100 ns to less than 50 ns.