Showing papers on "Parallel processing (DSP implementation) published in 1968"
TL;DR: An approach to the implementation of digital filters is presented that employs a small set of relatively simple digital circuits in a highly regular and modular configuration, well suited to LSI construction.
Abstract: An approach to the implementation of digital filters is presented that employs a small set of relatively simple digital circuits in a highly regular and modular configuration, well suited to LSI construction. Using parallel processing and serial, two's-complement arithmetic, the required arithmetic circuits (adders and multipliers) are quite simple, as are the remaining circuits, which consist of shift registers for delay and small read-only memories for coefficient storage. The arithmetic circuits are readily multiplexed to process multiple data inputs or to effect multiple, but different, filters (or both), thus providing for efficient hardware utilization. Up to 100 filter sections can be multiplexed in audio-frequency applications using presently available digital circuits in the medium-speed range. The filters are also easily modified to realize a wide range of filter forms, transfer functions, multiplexing schemes, and round-off noise levels by changing only the contents of the read-only memory and/or the timing signals and the length of the shift-register delays. A simple analog-to-digital converter, which uses delta modulation as an intermediate encoding process is also presented for andio-frequency applications.
236 citations
TL;DR: Two experiments on refractoriness were carried out in which the warning, first and second signals, S0, S1 and S2 respectively, were all single-valued, and the distributions of random intervals between S0 and S1, and S 1 and S 2 were the same.
Abstract: Two experiments on refractoriness were carried out in which the warning, first and second signals, S0, S1 and S2 respectively, were all single-valued, and the distributions of random intervals between S0 and S1, and S1 and S 2 were the same. In the first experiment the intervals in a trial were statistically independent: the null hypothesis, that the latencies of the two responses would be similar, was rejected, but the results were also found to agree with no existing alternative hypothesis. In the second experiment the intervals in a trial were conditionally related and the second response was found to be faster than in the first experiment. This is discussed in the context of the issue of serial or parallel processing of information.
13 citations
Proceedings Article•
01 Jan 1968
6 citations
TL;DR: A computer, the Visual Image Processor, is described which is designed to process visual images and reads and writes a signal which is a function of the reading signals written into the third storage system.
Abstract: —A computer, the Visual Image Processor, is described which is designed to process visual images. Images are read by a vidicon camera and stored in any of three identical cathode-ray electrostatic storage tubes. Two storage systems are read simultaneously, with the reading beams spatially displaced from each other, and a signal which is a function of the reading signals is written into the third storage system. The spatial displacement of the reading beams and the function are variable and under control of the computer operator.
5 citations
09 Dec 1968
TL;DR: The purpose of this work is to supply a simple method for definition and efficient control of a network for asynchronous parallel processing.
Abstract: The purpose of this work is to supply a simple method for definition and efficient control of a network for asynchronous parallel processing.
2 citations