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Showing papers on "Photomask published in 1973"


Patent
27 Jul 1973
TL;DR: In this article, an automatic alignment and exposure system is employed for aligning a pair of alignment marks on a semiconductive wafer with a corresponding pair of align points on a photomask to align the semiconductor with the photomasks.
Abstract: An automatic alignment and exposure system is employed for aligning a pair of alignment marks on a semiconductive wafer with a corresponding pair of alignment marks on a photomask to align the semiconductive wafer with the photomask. The automatic alignment and exposure system is also employed for directing exposure light through the alignment-mark-containing portions of the photomask onto corresponding portions of a photosensitive film of etch-resistant material on the semiconductive wafer to fully expose those portions of the photosensitive film and for directing exposure light through the photomask onto the entire unmasked surface of the photosensitive film to selectively expose the photosensitive film in accordance with the pattern of the photomask. Following this exposure operation, either the unexposed or the exposed portions of the photosensitive film are removed from the semiconductive wafer, thereby leaving an etchresistant mask that does not include the alignment marks of the photomask.

24 citations


Patent
Zingerman J1, Di Fazio J1, G Giuffre1
03 May 1973

2 citations


Patent
N Feldstein1, J Weiner1
22 Jan 1973
TL;DR: In this article, a method is proposed to cope with the ELECTROLESSLY DEPOSITING of a SEMITRANSPARENT FILM which is PREDOMINANTLY CUPROUS OXIDE OM a TRANSPARent SUBSTRATE and DELINEATING a PATTERN in the FILM by ETCHing.
Abstract: A METHOD COMPRISING ELECTROLESSLY DEPOSITING A SEMITRANSPARENT FILM WHICH IS PREDOMINANTLY CUPROUS OXIDE OM A TRANSPARENT SUBSTRATE AND DELINEATING A PATTERN IN THE FILM BY ETCHING.

2 citations


Journal ArticleDOI
TL;DR: In this article, a method for determining the location of the photomask array placement on slices that realizes the maximum number of available bars per slice in integrated circuit manufacturing is presented, taking into account the slice diameter and the flat length variation encountered in material.