Showing papers on "Programmable logic device published in 1979"

Detection of Faults in Programmable Logic Arrays

Abstract: A new fault model is proposed for the purpose of testing programmable logic arrays. It is shown that a test set for all detectable modeled faults detects a wide variety of other faults. A test generation method for single faults is then outlined. Included is a bound on the size of test sets which indicates that test sets are much smaller than would be required by exhaustive testing. Finally, it is shown that many interesting classes of multiple faults are also detected by the test sets.

Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)

Abstract: Programmable logic arrays (PLA's) are the logic implementation vehicle for many applications. Due to their regular structure, one is able to model and analyze many more of the likely physical faults than the conventional stuck faults considered for random combinational logic implementations. We investigate shorts between the lines and crosspoint defects (spurious absence or presence), as well as stuck faults in a PLA. It is shown that a complete crosspoint test set also detects most of all faults analyzed. The crosspoint-oriented test set is compact, easy to generate, and technology-invariant. For the test generation, the regularity of the PLA structure is utilized for ease of computation and for test set optimality. Groups of crosspoint defects are sensitized simultaneously. For each such fault group, a test configuration which contains the totality of the tests for the faults under consideration is efficiently generated. When the configuration is empty, there exists no test that detects the particular group of faults. A covering set of tests is then selected from the configuration. Our test generation method (TPLA) uses two basic and effective heuristics; they are the initial word ordering for processing and the use of look-ahead merit function whenever there is a free choice of values in a test input variables.

A High Density Programmable Logic Array Chip

Abstract: A programmable logic array (PLA) chip design using special array folding techniques and an on-chip bus structure has been developed. It overcomes the sparseness in conventional large PLA configurations. The design is a masterslice FET chip personalized for the particular application during processing. Software algorithms are used to map conventional PLA formats into the new structure. The techniques used provide improved logic function and performance for an FET array technology. Included are descriptions of the PLA architecture and the circuitry that was used.

A Programmable Logic Approach for VLSI

Abstract: This paper explores the use of a proposed programmable storage/logic array (SLA) chip as a general purpose universal logic element for digital computers. The SLA is compared to other programmable logic arrays in implementation and utilization, showing how it permits construction of complete digital subsystems on one chip without sacrifice in programmability. When compared with other contending very large-scale integrated technology (VLSI) approaches, such as microprogrammed processors and gate arrays, the SLA offers an attractive combination of cost, performance, and ease of implementation.

Logic Design of Programmable Logic Arrays

Abstract: Compared with random logic circuits, memory-type circuits are more suitable for LSI realization since their iterated structure of identical cells results in higher transistor density and higher yield A programmable logic array (PLA) is a read only memory (ROM) with programmable addresses and it is suitable for realizing logic functions with many unspecified input combinations For such a function, reduction of the number of input is possible in many cases Since the cost of a PLA is mainly determined by the number of pins and the chip, both of which are affected by the number of inputs, the reduction of the number of inputs is very important in PLA design On the other hand, the reduction of the number of product terms in a sum-of-product expression is important in conventional random logic synthesis Since there is a tradeoff problem between the number of inputs and the number of product terms, we give a design procedure by the following preference order: 1) minimizing the number of pins, 2) minimizing the number of product terms, 3) minimizing the number of circuits used in the PLA These factors also determine the area required for a chip

A 1500 gate, random logic, large-scale integrated (LSI) masterslice

Abstract: Describes the development for the bipolar gate array masterslice for custom designed logic. One chip is designed containing an array of standard logic gates which are then interconnected in a custom manner by using the various levels of metal on the chip. One such masterslice contains 1500 logic gates. The authors describe the physical organization of the chip, and the software package used to assist in simulating the logic, wiring the chip, and generating the patterns needed to test that specific logic function. The internal gate is described in detail, and a discussion of some of the design tradeoffs made is included. The peripheral level-shifting circuits used to interface with a T/SUP 2/L environment and an on-chip reference generating circuit are described. The testing philosophy used, and the package within which the chip is placed are discussed. The paper concludes with a description of the bipolar process used to manufacture the chip.

A study in the use of PLA-based macros

Abstract: Describes a study in which a PLA-based macro design of a small processor is carried out in the same technology as the original `random' logic design of the same processor. The objectives of the study were to determine gains or losses in `technology utilization' when a PLA-based approach is used to replace the more conventional `random' logic approach. The results in this case are a design of equal performance and density, with only one-third the power dissipation of the original design.

Multiple-function programmable logic arrays

Abstract: A programmable logic array which uses random-access memories to replace read only memories conventionally used in programmable logic arrays. The programmable logic array includes input and output terminals, an input register connected to the input terminals, an output register connected to the output terminals, first and second random-access memories, addressing means for sequentially and cyclically reading the random-access memories, a buffer register having an input to the output of the second random-access memory and an output connected to the input of the output register, a comparator having a first input connected to the output of the first random-access memory and a second input connected to the output of the input and output registers, the output of the comparator controlling the transfer of the contents of the buffer register and means for resetting the buffer register.

A subnanosecond masterslice array offering logic plus memory

Abstract: A 35mm2bipolar masterslice array offering up to 712 gate functions of subnanosecond random logic and 128 bits of RAM will be reported, citing its application to a 50MHz 4b microprocessor slice

Dynamically programmable logic circuits

Abstract: A programmable logic circuit is formed by at least one gate. The gate is formed by four logic circuits, one being a first exclusive NOR circuit having a first input, a second input and an output. A second exclusive NOR circuit having a first input, a second input and output is provided, the first input of the second exclusive NOR circuit being coupled to the first input of said first exclusive NOR circuit. An AND circuit having a first input, a second input and an output is also provided. The first input of the AND circuit is coupled to the output of the first exclusive NOR circuit and the second input of the AND circuit means is coupled to the output of the second exclusive NOR circuit. A third exclusive NOR circuit having a first input circuit, a second input circuit and an output circuit is provided the first input circuit of the third exclusive NOR circuit is coupled to the output of the AND circuit. The gate can selectively function as an OR, NOR, AND and NAND circuit depending on ONE and ZERO signal levels applied to the respective second inputs of the second and the third exclusive NOR circuits as program variables. One of the variables is applied to the first input of the first exclusive NOR circuit and to the first input of the second exclusive NOR circuit, another variable being applied to the first input of the second exclusive NOR circuit. By connecting the second input of the second exclusive NOR circuit to one of the inputs of the first exclusive NOR circuit, the logic circuit will operate as an exclusive OR or exclusive NOR circuit.

Use of memories and programmable logic arrays for asynchronous sequential circuits

Abstract: The design of asynchronous sequential circuits is commonly related to the problem of observing some specific timing constraints to avoid unreliable behaviour. State assignment and hazard-free construction of the combinational circuits for the state transition equations are the most essential topics to investigate. They contribute significantly to the design, particularly in comparison with that of synchronously operated systems. On the other hand, the application of digital circuitry for solving control tasks implies more and more asynchronous interaction between the controller and the controlled unit, and also the use of modern, highly-integrated modules. This paper investigates the possibility of applying arbitrarily chosen, but unique, codes for state assignments, using l.s.i. memories and programmable logic arrays for implementing more complex asynchronous sequential circuits than is possible with discrete or s.s.i/m.s.i. components. A basic model is derived to describe the time properties of such matrix arrays, and design rules are established to decide easily by some simple measurements, if a given module may be used in that application. The results of a broad investigation into available memories and field-programmable logic arrays show that reliable asynchronous sequential circuits may be implemented without having hazard problems and the need for special state-assignment procedures.

An Examination of the Cost Function for Programmable Logic Arrays

Abstract: Cost functions for combinational switching circuits are commonly defined as monotonically increasing functions of the number of gates and the number of inputs. The structure of programmable logic arrays (PLA's) is such that the cost is more aptly only dependent on gate quantity. The consequences of redefining cost for PLA's are studied with respect to covering algorithms. The major benefits are that a multiple output prime implicant (implicate) table can be viewed as a single output table and that minimal covers can be determined much more simply, especially for cyclic tables.

Digital Design With Standard MSI and LSI: Design Techniques for the Microcomputer Age

Abstract: Philosophy: Adapting the Job to the Bargain Components. The Goals of Digital System Design. Combinational Logic I: Traditional Logic Design. Combinational Logic II: MSI and LSI Logic Design. Sequential Logic Design. Nasty Realities I: Race Conditions and Hangup States. Programmed Logic I: Microcomputers. Programmed Logic II: Computer-Aided Programming. Programmed Logic III: Development Systems. Programming Logic IV: Microcomputer Hardware Design. The Time Dimension. Nasty Realities II: Noise and Reflections. Input/Output Devices. Use of Statistics in Digital Design. The Social Consequences of Engineering. Glossary. Index.

Emitter coupled logic programmable logic arrays

Abstract: Programmable logic arrays can be formed utilizing emitter coupled logic. Input terminals and control terminals associated with a programmable logic array module are coupled to the input terminals of a predetermined set of OR circuit means within the module. The outputs of the OR circuit means are coupled to various input terminals of a number of AND gates within the module. The outputs of the AND gates are coupled respectively to output terminals associated with the programmable logic array. The OR circuit means and the AND gates are coupled together in an emitter coupled logic format.

Introduction to Special Section on Programmable Logic Arrays

Abstract: IN AN earlier paper [1], aspects of LSI were discussed that provide strong motivation for using programmed logic arrays for implementation of computer functions. These factors include extended use of a single chip design, the necessity to design for function, effective fault analysis and testing, and minimal design errors and changes. The approach to LSI exemplified by PLA's will continue to be useful in VLSI, since the factors cited for large-scale integration will be even more prominent in the very large-scale integration environment with its demand for more on-chip function.

Electronic logic circuits

Abstract: Two-state systems * Basic elements of combinational logic * The design of combinational logic circuits * Sequential logic elements * Sequential logic systems * The design of sequential logic circuits * Electronic logic circuits * Large logic networks * Application specific integrated circuits (ASICs) * Appendices * Bibliography * Index.

Semiconductor logic circuit device using junction short-circuit type programmable logic cell

Abstract: PURPOSE:To enable to obtain the logic circuit function in high speed by the constitution of internally shortened P-N junction between the first emitter and base, in the transistor constitution in a cell. CONSTITUTION:The device consists of the group G1 of 2X3 sets of logic cells M11, M12; M21, M22; M31, M32 and the group G2 of 2X2 sets, M11, M12; M21, M22. The P-N junction between the emitter and base of the cells M11, M12 and M32 of the group G1 is internally shortened (equivalent to diode D), and the P-N junction between the emitter and base is internally shortened by giving a pulse as opposite direction as the P-N junction to the electrodes and wiring layers 14, 15 relating to the transistor constitution Q' of cells M11, M12, M21 of the group G2. Accordingly, even if the constitution Q' of the group G2 has the capacity CS' to the P-N junction, since no CS' to the logic cell connected to the logic output line Yi of the group G2 is connected, the logic circuit function can be obtained in higher speed in comparison with conventional devices.

Semiconductor memory circuit

Abstract: PURPOSE:To realize the programmable logic circuit high in the reliability, by adding readout transistor to FF constituted with n channel MOSFET pair through taking two fuses as loads CONSTITUTION:The readout transistor Tr9,10 are added to FF taking fuses 7 and 8 as loads and constituted with n channel MOSFET's 5 and 6 Thus, the information can be stored in RAM memorizing it without non-volatile operation, then the check of the content of information can sufficiently be made, and the programmable logic circuit having high reliability can be realized, which can store the information once writtern in semi-permanently

Applications Of Programmable Logic Arrays To Video Rate Image Processing

Abstract: Programmable Logic Arrays (PLA's) are digital electronic devices capable of performing complex logic functions at very high rates - up to 20 million operations per second. They are available in many configurations including several types that can be field programmed using simple and inexpensive equipment. They are thus ideal devices for implementing several types of video rate image processing algorithms, particularly those algorithms that involve a high degree of adaptability or binary decision making. This paper describes the technology and operation of PLA's and details several representative image processing applications, including an adaptive differential signal compression algorithm, a gradient generator, and an edge continuity detector.

Iterative Realization of Multivalued Logic Systems

Abstract: The realization of multivalued combinational functions and sequential machines by using arrays of one type of cells is considered. The algebra used for the multivalued logic system has two binary operations and a set of unary operations. Each of these operations is realized by a cellular array. The cells are combinational and implemented by using binary logic gates. The cells are also designed so that all unrestricted multiple faults in arrays of these cells are detectable. Multivalued combinational functions, storage elements, and sequential machines are realized by interconnecting the arrays realizing the operations.