Showing papers on "Redundant code published in 1984"

A compiler for lazy ML

Abstract: LML is a strongly typed, statically scoped functional Language with Lazy evaluation. It is compiled trough a number of program transformations which makes the code generation easier. Code is generated in two steps, first code for an abstract graph manipulation machine, the G-machine. From this code machine code is generated. Some benchmark tests are also presented.

Method and apparatus for generating a translator program for a compiler/interpreter and for testing the resulting translator program

Abstract: A translator writing system develops a translator program capable of transforming a user's source code into object code. The language of the source code is summarized in a unique form, namely, a Backus-Nauer Form (BNF). This BNF form of the source code is utilized by the translator writing system to transform the source code into object code. The BNF form takes into account the attribute specifications associated with the language of the source code and the interaction of the attribute specifications in the grammar of the language of the source code. The translator writing system includes a valid testcase generator for testing the developed translator program utilizing every possible correct program statement in the language of the user's source code. The translator writing system further includes an incorrect, invalid testcase generator for testing the developed translator program utilizing every possible incorrect, invalid program statement in the language of the user's source code. As a result, the amount of effort required to test the developed translator program has been significantly reduced.

Method of code changing for electronic lock

Abstract: A combination changing method is used in an access control system which includes one or more keys encoded at a central console with a function information code, a key identification information code, an operation select information code and a two-field key combination information code and one or more locks having at least one memory level in which a lock identification information code and a lock combination information code are stored. A key is initially inserted into a selected lock and the data from the key is transferred to the lock. The lock identification information code is first compared with the key identification information code. If there is no correspondence, power to the lock is turned off for a set period of time. If the identification information codes correspond, a test field of the key combination information code is compared with the lock combination information code. If these correspond, the lock opens. If the identification information codes correspond but the test field of the key combination information code and the lock combination information code do not, then the operation select information code is used to select from a predefined set of operations (logical and/or arithmetic and/or other). The operation selection is then performed on an operand field of the key combination information code. This results in a computed combination information code which is compared with the lock combination information code. If this comparison is successful, the test field of the key combination information code is stored in the lock in place of the lock combination information code and the lock opens.

Central processor utilization monitor

Abstract: Data relative to code instruction use of a central processor unit (CPU) is collected by accumulating counts of code instructions to be executed upon termination of a clock interrupt process over a predetermined interval. Information stored on occurrence of a clock interrupt pulse is evaluated to determine if the code instruction is one under evaluation. If the code instruction is one under evaluation, a count in an associated memory location is incremented. Upon termination of the predetermined interval, the data is read out in histogram form. The data in the histogram is relative to the virtual addresses of the code instructions and, therefore, directly useable by a programmer to evaluate the code use of the CPU without the need for costly and time consuming data unmapping.

Using dynamic programming to generate optimized code in a Graham-Glanville style code generator

Abstract: We have performed an investigation of using a dynamic programming to generate optimized code in a Graham-Glanville style code generator We use Earley's algorithm rather than an IR algorithm for parsing in the code generator Not only does the use of Earley's algorithm make the construction of the code generator very easy it allows the selection of optimal code by dynamic programming (using a modification of the technique developed by Lvon) We compare two implementations of this technique to conventional hand-coded code generators using a subset of BASIC as the source language Further we discuss the use of this technique in an experimental C compiler.

Graham/glanville code generators (compiler, parser, programming language)

Abstract: A desirable organization for a compiler has a target machine independent, source language dependent front end, and a target machine dependent, source language independent back end. The two parts communicate through an intermediate representation (IR). The back end, also called a code generator, translates the IR to target machine instructions. The Graham-Glanville code generation method can be used as the basis for the code generator. The method uses a grammar of linearized instruction patterns to describe the target machine. An LR-like parser is used to cover the IR with instruction patterns. This dissertation develops the necessary techniques to make the Graham-Glanville approach a practical code generation method. We describe a major experiment in which a production quality Graham-Glanville code generator was developed, retargeted to three different target machines, and used to translate real programs written in "C", Pascal and Fortran into good code for those machines. In the course of the experiment, we tested new code generation ideas, and developed several significant improvements to the method. A methodology is given to write machine description grammars to exploit the structure of the target machine. A syntactic approach has been developed, in which almost all semantic attributes required to select code are encoded directly into the grammar. This encoding simplifies the code generator, although it increases the size of the grammar. Tools are described that compensate for the grammatical size, and ease designing the grammar. The tools exploit properties of the IR, and encode attributes into the grammar. Despite the large grammars, the parser is quickly constructed by exploiting the observed properties of machine description grammars. A discussion of instances in which less than optimal code can be produced, and remedies for those instances is given. The aspects of the code generator design that facilitate retargeting are described. They include the use of IR transformations and the centralization of machine dependent information. The retargeted code generators are compared with one another and with another code generator for the same front ends. An evaluation is given that demonstrates the success of our methods and the practicality of the Graham-Glanville approach.

Pipeline-controlled information processing system for generating updated condition code

Abstract: The system includes a fetching circuit which sequentially fetches instructions to be executed. Certain of the instructions require that a predetermined condition code be present prior to being executed and certain of the instructions cause a condition code to be generated as a result of their execution. Condition code generators are provided for generating condition codes in response to execution of the instructions causing generation of condition codes. A circuit is also provided which is responsive to the sequentially fetched instructions for individually determining which of the instructions is to cause generation of a condition code, and which of the condition code generators is to generate a condition code for each of the determined instructions. The determined condition code generators are monitored, and a decision is made as to when a valid condition code has been generated by the monitored generator. A signal is produced when a valid condition code is generated. A decision circuit is connected to the fetching circuit for deciding which of the instructions requires the presence of a condition code prior to being executed. The decision circuit is connected to receive the signal indicative of a generated valid condition code, and is connected to inhibit the fetching circuit when a next sequential instruction requires the presence of a valid condition code and the signal is not present.

Pipeline-controlled type information processing system

Abstract: The PIP system comprises a plurality of condition code generation units, each having a counter section and an operating section for operating the counter section in the event of generation of a condition code. A condition-code-updating instruction discrimination unit discriminates, in response to every instruction, one of the condition code generation units which is to generate a condition code, holds a result of the discrimination, and operates one of the counter sections associated with the result of the discrimination. A condition code determination decision unit identifies counts held by the plurality of counter sections and the result of the discrimination to produce a signal indicative of a determined state of a condition code and a condition code. This system achieves fast execution of condition code reference instructions and is capable of seeing whether or not a condition code has been determined by constantly monitoring a condition code generation mechanism which is used by the latest condition code update instruction being executed on the pipeline. As a result, a subsequent condition-code-reference-instruction need not await the determination of the condition code of the previous instruction executed.

Method of detecting synchronization errors in a data transmission system using a linear block code

Abstract: In a data transmission system messages can be transmitted in the form of sequentially linked modified code words of a linear block code, the modified code words being produced by combining the code words formed from the data with a protection word. When such modified code words are interleaved bit-wise in order to recognize random errors, the sequence of code words of the transmitted message may be changed after de-interleaving at the receiver, by bit shift, due to faulty synchronization of the transmitter and receiver. In order to recognize this, each code word is linked to a protection word which identifies its position within the message. The modified code words thus obtained are interleaved bit-wise, transmitted and de-interleaved again at the receiver. Each word thus obtained at the receiver is combined with a check word identifying its position within the message. The protection words and the check words are chosen so that the key words produced by combining them are in code word sub-classes which are not used for decoding.

Code generation by coagulation

Abstract: This paper describes a new approach to code-generation. The central tenet is that there must be a more intimate coupling between register allocation and instruction selection than exists in present-day technology. This is achieved by generating code in very small regions and gradually coalescing the part of the program that is "compiled".

Digital remote controller

Abstract: PURPOSE: To decide whether a key is kept in a depressing state, or the key is re- depressed at a reception side, when the same data code is received, by performing transmission by varying the code constitution of the end code of a remote control transmission code corresponding to the number of times of transmission operations such as the depression of the key, at a transmission side. CONSTITUTION: Each bit of a custom code 2, an instruction code 3 constituting the transmission code is expressed as information '1' or '0', based on the position of one data pulse 22 inserted at every synchronizing pulse 21 of constant cycle. At the transmission side, the number of times of the re-depression of the key are conuted by a counter, and the end codes 4a, 4b, and 4c having the code constitution corresponding to counted values 1, 2, and 3, in one to one, are generated, and are transmitted behind the custom code 2 and the instruction code 3. At the reception side, the custom code 2, the instruction code 3, and the end code 4a, 4b, or 4c are received and decoded, and when the custom code 2 coincides with the one allocated to its own equipment, and also, the code constitution of the end code is different from the one received precedingly, it is decided as the re-depression of the key, and a controlled system executes an instruction. COPYRIGHT: (C)1988,JPO&Japio

Programming with small blocks

Abstract: Programming style is a highly personalized characteristic of programs. Modular and block structured programming techniques provide many standards for good programming. These techniques are used to develop well designed but only marginally readable code. Similar organizational techniques are not typically applied to code inside subroutines, which is either too small or too specific to be further broken down into subroutines. The result is often obscure subroutine code that makes the maintenance programmer's job extremely difficult. Presented here is a styling technique for intra-subroutine code that groups program statements into "small BLOCKS" of function or conditional constraints. It is shown that this style of formating subroutine code can greatly improve the readability of the average program. The technique is demonstrated in Pascal, C, and Lisp.

System for processing error

Abstract: PURPOSE:To perform proper error processing with an information processing device of microprogram controlling system, by adding a redundant code and adopting the frequency of error which occurred in the course of error processing routine as data to be recorded. CONSTITUTION:Data required for making error processing by means of a microprogram are stored in a register file after a redundant bit is added. At the time of reading out it is detected by using the redundancy bit that correct data is to be reproduced by the microprogram or reproduction of the correct data is not possible when the reproduction is not possible.

RFQ simulation code

Abstract: We have developed the RFQLIB simulation system to provide a means to systematically generate the new versions of radio-frequency quadrupole (RFQ) linac simulation codes that are required by the constantly changing needs of a research environment. This integrated system simplifies keeping track of the various versions of the simulation code and makes it practical to maintain complete and up-to-date documentation. In this scheme, there is a certain standard version of the simulation code that forms a library upon which new versions are built. To generate a new version of the simulation code, the routines to be modified or added are appended to a standard command file, which contains the commands to compile the new routines and link them to the routines in the library. The library itself is rarely changed. Whenever the library is modified, however, this modification is seen by all versions of the simulation code, which actually exist as different versions of the command file. All code is written according to the rules of structured programming. Modularity is enforced by not using COMMON statements, simplifying the relation of the data flow to a hierarchy diagram. Simulation results are similar to those of the PARMTEQ code, as expected, becausemore » of the similar physical model. Different capabilities, such as those for generating beams matched in detail to the structure, are available in the new code for help in testing new ideas in designing RFQ linacs.« less