Showing papers on "Registered memory published in 1974"

Memory access technique

Abstract: In a digital computer system having a main memory operable at a first speed, a high speed buffer operating at a second speed for temporarily storing selected portions of the main memory, an associative memory for temporarily storing selected main memory addresses and comparing the stored addresses with a newly received address in a read/write operation to generate comparison data, a read only memory a bit configuration reflecting an algorithm, connected to the associative memory for generating a new order of priority for the memory address stored in the associative memory, and a storage unit connected from the read only memory for storing that order of priority for subsequent feedback to the read only memory in a subsequent cycle as a previous order of priority.

Advanced array transform processor with fixed/floating point formats

Abstract: A special purpose hardware peripheral which acts as a high speed auxiliary processor. Read-only memory controllers and floating point arithmetic are used to accurately produce high speed processing of arrays of data, thus effectively increasing the processing power of the minicomputer. The system employs an internal memory of two independent sections with means for parallel (simultaneous) operation; employing one section in conjunction with an arithmetic unit while employing the other section in conjunction with data transfer to and from CPU main memory. Three ROM controllers are employed for controlling this simultaneous operation of the memory, the arithmetic unit and the data transfer to and from CPU main memory.

Reliability of random access memory systems

Abstract: A digital memory is configured as a hierarchical system with at least three levels. The first level consists of a main bus and interfacing for one or more main memory units; the second level consists of a separate second level bus in each main memory unit with a plurality of memory frames independently interfaced to each bus; and the third level consists of a separate third level bus in each memory frame with a plurality of memory storage blocks independently interfaced to each bus. Virtual addressing is employed in which the whole of each address is decoded in the individual memory block which includes for the purpose soft-ware settable registers containing identification numbers.

Method for providing a substitute memory in a data processing system

Abstract: A method for substituting one memory module for another, faulty, memory module comprises designating and marking a memory module as the substitute module, which, upon detection of a fault in the other memory module, is inhibited from responding to its own address when called, and responds to the address of the faulty module whenever the latter is called.

Method and apparatus for assisting in debugging of a digital computer program

Abstract: The specification discloses a technique for assisting in the detection of errors and malfunctions in the operation of a digital computer program. The system includes circuitry for connection to the back plane of a digital computer for receiving representations of the program instructions executed by the computer. A memory normally connected to a first in-first out configuration includes a plurality of series connected stages connected to receive the representations, each of the representations normally being sequentially stored in successive ones of the stages and then transferred to the output of the memory and dumped. Mode selection circuitry is operable to interconnect the system in the sentinel, breakpoint or snapshot modes. In the sentinel mode, in response to a computer malfunction, the circuitry is operable to connect the memory output to the memory input to form a first in-last out memory configuration to store the instruction representations in the memory. In the breakpoint mode, circuitry is operable to terminate operation of the computer and to connect the memory output to the memory input to store the contents of the memory upon the execution of a preselected program instruction. In the snapshot mode, the circuitry is operable to connect the memory output to the memory input to store the contents of the memory upon the execution of preselected program instructions, without terminating operation of the computer. A display is provided to selectively visually display the stored contents of the memory in order to assist in detecting errors and malfunctions in the operation of the computer program.

Memory control circuitry

Abstract: A control circuit for reading from, and writing into, a random access memory into which successive data entries are stored at addresses in sequential binary order. A scan generator provides a repeated sequence of all sequential binary order addresses to the memory, and the write-enable input of the memory is controlled in synchronism with the memory addressing by continuously comparing the desired addresses of next-date entries with the scan generator addressing output, and enabling the write function of the memory when these addressing signals are the same.

Random access memory shift register system

Abstract: A random access memory array wherein each storage cell includes an input, an output, a write control and a read control is coupled to a commutator system, the random access memory array is thereby operated by the commutator system to provide a shift register system. Various embodiments of the random access memory shift register system of the invention provide many advantages over conventional shift register systems including flexibility; high, low or variable speed; high density; and low power.

Memory unit for connection to central processor unit and interconnecting bus

Abstract: In order to incorporate a very high speed memory subsystem into a computer system utilizing unified bus architecture, memory control apparatus associated with the very high speed memory is provided with a first port communicating directly with a system central processor and a second port interfacing with the unified bus. The memory control apparatus may include means for systematically refreshing volatile high speed memories. Multiple processor systems may be realized by taking advantage of the dual port characteristics of the very high speed memory subsystems associated with each central processor.

Mnos/sos random access memory

Abstract: A non-volatile random access memory comprising silicon on sapphire MNOS memory elements incorporated in an array having a plurality of like memory cells. Each cell is configured to provide charge enhancement symmetrically in both the read and write modes to restore or refresh the threshold voltage states of the memory elements and particularly the high or more negative threshold voltage state.

Memory for use in a computer system in which memories have diverse retrieval characteristics

Abstract: A memory unit for use with a central processor unit in a data processing system. To retrieve data from the memory unit, the central processor unit energizes an appropriate one of several memory retrieval control signal conductors and memory address signal conductors to initiate a memory cycle during which the memory unit transmits an address acknowledgement signal and data signals back to the central processor unit. The memory unit has a characteristic retrieval interval during which the memory cycle is performed to retrieve data. Each memory retrieval control signal corresponds to a different category of characteristic retrieval interval. When the memory unit transmits the data signals, it transmits a data control signal which is delayed with respect to the address acknowledgement signal by a time interval that is directly related to the characteristic retrieval interval for the memory unit. If a memory unit has a certain characteristic retrieval interval, there also is included a circuit for transmitting a data warning signal a fixed time before the data control signal.

Dynamic Memories with Rapid Random and Sequential Access

Abstract: We propose a new architecture for dynamic memories in which the contents of any cell in memory can be accessed by applying a sequence of two primitive memory operations. The advantage of our memory over previous designs is its fast sequential access. Any word in an n cell memory can be accessed in 0(log n) steps. However, once two consecutive words have been accessed, following words can be accessed in one step per word.

Semiconductor block-oriented read/write memory

Abstract: A block oriented read/write memory (BORAM) employs a known type of variable threshold insulated gate field effect transistor memory cells. The memory cells are arranged on a common substrate in an array of horizontal block rows and vertical word columns. A block decoder selects one block row for a given operation in which information is simultaneously read out of, or written into, each memory transistor in the selected block from a parallel/serial shift register. Information is multiplexed into or out of the shift register in serial fashion while the memory transistors are being subjected to a four-phase operating sequence utilizing a ''''channel shielding'''' technique.

An Organization for a Highly Survivable Memory

Abstract: A memory organization is considered for which a large number of faults can be tolerated at a low cost in redundancy. The primitive element in the memory is a large-scale integrated (LSI) chip that realizes a section of memory, b bits wide by y words long, together with an address decoder for the y words. The chips (including spares) are connected via a switching network so that the memory can be reconfigured effectively in the presence of chip failures. The main results of the paper relating to the switching network are as follows.

Computer memory read delay

Abstract: Disclosed is a digital computer memory system which coordinates between plural memories such that information recall from memories having different inherent access times results in a flow of only relevant data to the processor; this is accomplished in, for instance, a dual memory system, by synchronizing the operation of the memories such that the normal clock pulse of the computer strobes the output register of the faster (i.e., "normal") memory but a delayed clock pulse strobes the output register of the slower memory. Thus, because of the delayed strobe, the latter, as well as the former, has time to complete an access requested by the processor, and, consequently, transfer to the processor of incorrect or meaningless information is avoided. This system is incorporated in the computer in the form of additional registers, memory elements, gates and arithmetic circuits, which recognize addresses as falling within either memory, energize the appropriate memory and excite it for read out with either a normal or delayed strobe as determined by its identification as the fast or slow memory, respectively.

Expanded memory paging for a programmable microprocessor

Abstract: For a serial-bit, programmable microinstruction processor having serial-byte internal transfers, an expanded-memory addressing apparatus and method is provided by the incorporation into the processor system a plurality of external memory units and a selection and transfer circuitry for accessing external memory space from within the processor. The accessing of external memory locations may be controlled by programmed memory access command instructions. These instructions may be operated upon by decoding components and buffer storage components to make available, concurrently, the entire contents of a particular one of the external memory units. Once a particular memory, or page is selected, a location within that page may then be addressed by memory address registers within the base processor.

Reconfigurable decoding scheme for memory address signals that uses an associative memory table

Abstract: This specification describes an associative memory decoder for a memory system in which the units in the memory system are reconfigurable both in size and in number. The decoder is designed to take an address for that memory system and address memory space in the memory system irrespective of the amount of storage in the system so that the decoder has to change as memory capacity is added or subtracted from the memory system.

Memory and memory addressing system

Abstract: Memory system employed in a time compression scanner for monitoring telephone lines. Digital samples are written into the storage locations of a memory during one memory addressing period, and these samples are read out during the next memory addressing period, but in a different order from the order in which they were entered. As each sample is read out, it is replaced by a new sample which is to be read out during the subsequent memory addressing period. The memory address for writing in and reading out each sample is controlled by a series of flip-flops. Clock pulses are directed to a different one of the flip-flops during each memory addressing period in a recurring sequence of addressing periods in order to cause the storage locations to be addressed in a different order during each memory addressing period.

Data processor reorder random access memory

Abstract: Random access memory addressing system for mapping data into a memory according to one schema and retrieving the stored data according to another schema using minimum storage locations.

Memory system including addressing arrangement

Abstract: Read only memory system employing four arrays of memory elements, each memory element storing 256 8-bit word segments. Each memory element has address input connections for selectively addressing each word segment and a memory element select connection for enabling the memory element. Each memory element operates in response to a clock pulse at its clock input during a signal at its select connection to read out in parallel the 8 bits of the word segment addressed by signals at the address input connections. Address information bits are received in parallel and applied to a decoding arrangement. The decoding arrangement includes a group of gates which couple a first portion of the address bits to the address input connections of all the memory elements of the system. The decoding arrangement also includes a first decoder coupled to the select connections of all the memory elements of the system for enabling particular memory elements of each array as determined by the second portion of the address bits. A second decoder in the decoding arrangement produces a signal at one of four outputs as determined by a third portion of the address bits. These four outputs are connected to a source of clock pulses and gate a clock pulse to one of the four arrays depending on which output has the signal present. The clock pulse is applied to the clock inputs of all the memory elements of that array.

System for modifying a logic controller instruction set

Abstract: A programmable logic controller includes a read/write memory for storing multi bit instructions which direct computations in the controller in response to a programming keyboard module connected to the controller for encoding instructions to be stored in controller memory. Keyboard commands transfer instructions from the module to said memory in an ordered array. Instructions are read from memory serially, cyclically and non destructively for operation of the controller. A keyboard insert command inserts a new instruction at a designated address in memory and sequentially shifts each serially accessed instruction in memory stored at an address beyond the designated address to a memory address once removed.

Fault-tolerant memory organization: Impact on chip yield and system cost

Abstract: A method is presented for utilizing the loop-to-loop functional independence of multiloop bubble memory devices. The locations of the defective loops are stored in inexpensive flag chips which are located at rows of memory chips. A statistical analysis is presented to determine the number of redundant loops needed on each memory chip to guarantee a given data capacity. A memory System cost reduction of up to 50% is demonstrated for the fault-tolerant scheme chosen as a model.

Memory clocking system

Abstract: A solid state memory employs a plurality of memory cells each capable of storing either of two different binary values. The memory cells require periodic application of a refresh pulse to the memory cell to, without rewriting, enhance at least one of the two different binary values which the memory cells can store, in order to prevent loss of that binary value over a period of time. The reliability of the memory is improved by supplying a refresh signal which includes a plurality of refresh pulses in each memory cycle.

Circulating shift register memory having editing and subroutining capability

Abstract: A circulating shift register memory used in a hand-held programmable calculator is described in which the informational words of data contained therein are edited by selectively including one-word storage register in or excluding such registers from the circulation path of the memory. The selectable storage elements contain new or discardable data at the time of their inclusion in or exclusion from the circulation path. Logic circuitry for controlling the number of storage elements in the circulation path is responsive to unique control words which share memory space with the information words. The same circuitry and a similar method are used for subroutining in the same memory.

Memory system with bytewise data transfer control

Abstract: Memory system comprising a first memory and a second memory, in which memories a plurality of memory elements are arranged according to word locations and can be addressed by an address signal per word location, further comprising for each memory an instruction line for read and/or write instruction signals, driving devices and terminals in each memory which are interconnected by a data path line, and a control device capable of generating the instruction signals for addressing word location in the first memory for transferring information associated therewith as an information word via the data path line between the two memories.

Data insertion in the speech memory of a time division switching system

Abstract: A system is disclosed for enabling control data to be inserted into a speech memory of a time division switching system in place of speech samples. The control data may then be used for maintenance and test purposes. In the system, a control memory is provided with cells associated with a speech memory row which normally stores a speech sample. Depending upon the condition of the appropriate control memory cells, either the speech sample or the control data is inserted into the speech memory row. Control circuits provide appropriate switching signals during half-time of the TDM elementary time.

Circuit Array and System of MAOS Type Fully Decoded Electrically Alterable Read Only Memory-Ic

Abstract: A new memory circuit array and a system of fully decoded electrically alterable read only memory-IC's (EA-ROM-IC) have been investigated in details by using a non-volatile MAOS memory cell. EA-ROM-IC's based on two fundamental memory circuit methods consisting a 1 MOS-CELL/1 BIT circuit system with an isolated row address decoder and a 3 MOS-CELLS/1 BIT circuit system without the address isolation structure have been designed and fabricated. The detailed electrical properties of these memory systems are discussed in addition to the fundamental memory array and circuit design parameters.

Driver cell with memory and shift capability

Abstract: A circuit including a memory cell which has both memory and shift capabilities. The circuit may operate as a driver circuit which can store information in a memory cell or feed-forward information in order to shift information or data from one cell to another. A driver function is associated with the circuit wherein the data or information shifted from one cell to another is not diminished or deteriorated.

High-speed random access memory

Abstract: A bipolar RAM has increased speed through use of nonsaturating voltages and improved read/write capabilities provided by memory cell and isolation circuit which functions as a sense amplifier. An output buffer including constant current means provides an output responsive to the signal from the memory cells taken through the isolation circuitry.

Magnetic-wire memory system

Abstract: A magnetic-wire memory system of a balanced, address selecting matrix type comprises a first and a second memory stack each including the same number of information lines and word lines both arranged in a symmetrical manner, a word driving circuit provided commonly for these memory stacks for driving a word line, a differential amplifier to receive output signals from these stacks, a plurality of switching circuits respectively connected to all of the information lines, and a bit driving circuit to drive two information lines included respectively in said first and second memory stacks through resistors and the corresponding switching circuits, whereby when read-out, an information signal including noise and only noise are delivered from these memory stacks to the differential amplifier, and the noises are therein cancelled.