Showing papers on "Remainder published in 1982"

Generalized Polynomial Remainder Sequences

Abstract: Given two polynomials over an integral domain, the problem is to compute their polynomial remainder sequence (p.r.s.) over the same domain. Following Habicht, we show how certain powers of leading coefficients enter systematically all following remainders. The key tool is the subresultant chain of two polynomials. We study the primitive, the reduced and the improved subresultant p.r.s. algorithm of Brown and Collins as basis for Computing polynomial greatest common divisors, resultants or Sturm sequences. Habicht’s subresultant theorem allows new and simple proofs of many results and algorithms found in different ways in Computer algebra.

Inferring a sequence generated by a linear congruence

Abstract: Suppose it is known that {X0, X1,...,Xn} is produced by a pseudo-random number generator of the form Xi+1 = aXi + b mod m, but a, b, and m are unknown. Can one efficiently predict the remainder of the sequence with knowledge of only a few elements from that sequence? This question is answered in the affirmative and an algorithm is given.

An asymptotic expansion of the solution of a second order elliptic equation with periodic rapidly oscillating coefficients

Abstract: This paper studies the asymptotic behavior of the fundamental solution of the equation specified on the whole space , , as . The coefficients are periodic functions which satisfy the conditions of ellipticity, symmetry, and infinite smoothness.The main result is the construction of the asymptotics of in the form where is an arbitrary positive integer, the are homogeneous of degree in the first argument and periodic in the remaining arguments, and for the remainder term on the set , , the estimate holds, where the constants are independent of , , and .Bibliography: 9 titles.

Pipelined operation unit for vector data

Abstract: In an operation unit wherein a series of data is sequentially applied, a predetermined operation is performed in synchronism with the input data in a pipelined manner, and the predetermined operation is applied to an input data and the result of the predetermined operation for a preceding input data. There are provided a plurality of partial operation devices which respectively compute a plurality of different partial data of a result data to be obtained as a result of the predetermined operation, and when one of the partial data is obtained, the one partial data is immediately used for the operation for the subsequent input data. Consequently, the operation for the subsequent input data can be started before the operation for the remainder of the partial data of the preceding input data is completed.

Data receivers incorporating error code detection and decoding

Abstract: A data receiver is required to detect successive 50-bit frames of data which are transmitted without any pause between frames and with a start bit value of 1 as the only start-of-frame indication. Error detection and correction is obtained by appending at the transmitter a 13-bit check word to 36 data bits (and the start bit), the value of the check word being chosen such that division of the error-free composite 49-bit code word by a predefined generator polynomial yields a syndrome (remainder) of zero. Calculation of a new syndrome value by the receiver at the speed necessary during initial frame synchronization (i.e. for each successive bit) is effected with an iterative procedure in which the previous syndrome value is left-shifted one place and the newly received digit is appended to it; the generator polynomial is added to the result by modulo-2 arithmetic if the most significant digit of the shifted syndrome word is a 1; and the remainder of -2 49 divided modulo-2 by the generator polynomial is added to the result of the previous step by modulo-2 arithmetic if the digit received 49 bits before the newly received digit is a 1.

Digital matrixing system

Abstract: A matrix for digital video signals separates each coefficient into a binary part and a remainder. The binary part can be implemented very simply by a hardwired right shift. The remainder can be implemented using a ROM. Less ROM memory space is required than for implementing the entire coefficient in a ROM.

Distribution of integral points on the determinant surface

Abstract: One obtains an asymptotic formula with remainder term for the number of second-order integral matrices with an increasing determinant, belonging to a given region of the discriminant surface and to a given residue class. The results are more accurate than in A. M. Istamov's paper (this issue, pp. 14–17) and are obtained in a somewhat different manner. The presentation is more detailed.

Asymptotic expansion of the Hankel transform with explicit remainder terms

Abstract: be the K-transform off In recent years various techniques have been developed to obtain explicit expressions for the remainder in the asymptotic expansions of functions defined by (1.1) as x —> oo. A survey of such techniques is given by Wong [17]. It is well known that under some reasonable assumptions on / and K, the Parseval relation for the Mellin transform provides a powerful tool for obtaining the asymptotic expansion of F(x). However, until recently the potential of this technique for obtaining an explicit expression for the remainder had been largely overlooked. If M[K, s] is the Mellin transform of K evaluated at s, M\_f 1 — s] is the Mellin transform of/evaluated at 1 — s, and the integrals defining these transforms converge in a strip containing the line Re s = c then, formally, by the Parseval relation,

Analog/digital converter using remainder signals

Abstract: A fast A/D converter using a series of A/D modules, each of which determines one or more bits of the total digital output and generates a remainder signal which serves as the input signal for the next modules in the series. In each module, one or more comparators compare the input signal to one or more predetermined bias potentials. The output of the comparators is used to generate the digital output of the module. The output of the comparators is also used to operate switches which apply either zero or the highest bias potential which does not exceed the input signal to a subtraction circuit. The subtraction circuit finds the difference between the input signal and the selected bias potential. In one embodiment this difference can be used as the remainder signal for the next module, or the difference can be multiplied before being used. Several circuits for avoiding output ripple are also disclosed. In another embodiment, the remainder signals are repeatedly recirculated through the same A/D module.

Remainder Terms in Numerical Integration Formulas of the Sphere

Abstract: The purpose of the present paper is the study of formulas for numerical computation of integrals over the (unit) sphere. The theory of Green’s functions on the sphere with respect to the (Laplace-)Beltrami-operator is the main tool. General cubature formulas are considered. Estimates of the truncation error are given. Best approximations are discussed for regular figures on the sphere.

Error correction system

Abstract: A method and apparatus for correcting single bit errors in data stored in a first memory includes a dynamic shift register for dividing data by a polynomial during the time the data is being written into the first memory resulting in the generation of a remainder which is stored in a second memory. When reading the data from the first memory, the data is again divided by the same polynomial. The remainder generated by the second division is compared with the remainder stored in the second memory. If the remainders do not match, indicating an error was introduced into the data during storage or retrieval of the data in the first memory, the remainder stored in the second memory is shifted into the dynamic shift register and followed by the shifting of a number of zero bits into the shift register which is equal to the maximum number of bits in the data located in the second memory. As each zero bit is shifted into the shift register, a bit counter is incremented and the output bit of each stage of the shift register is examined. When the output of all the stages in the shift register except the last stage is zero and the last stage contains a binary bit one, the count of the bit counter points to the bit location in the data stored in the second memory locating the bit that is in error.

On the Lagrange Remainder of the Taylor Formula

Abstract: (1982). On the Lagrange Remainder of the Taylor Formula. The American Mathematical Monthly: Vol. 89, No. 5, pp. 311-312.

Asymptotic formulae with remainder estimates for eigenvalues of schrödinger operators

Abstract: (1982). Asymptotic formulae with remainder estimates for eigenvalues of schrodinger operators. Communications in Partial Differential Equations: Vol. 7, No. 1, pp. 1-53.

Cellular division circuit

Abstract: An improved cellular division circuit is disclosed for performing divisional computation faster than prior art systems. The cellular division circuit includes a first adder for adding a dividend and a divisor thereby forming a first remainder and a second adder for adding the dividend with the complement of the divisor thereby forming a second remainder. The circuit includes means for complementing the highest order bit of each of the first and second remainders thereby forming first and second quotient bits. A selector circuit is provided for selecting the first or second quotient bits and for selecting the first or second remainders in response to a first selection signal.

Cubature Remainder and Biorthogonal Systems

Abstract: Error estimates for cubature formulas are usually given in terms of higher derivatives (Peano-Sard) or in terms of analyticity properties (Davis-Hammerlin). The approximation method has found little attention. We present the latter method in a generalized and refined form, based on biorthogonal systems (BOGS). The degrees of approximation and coefficient estimates connected with a BOGS lead to rather good and versatile inequalities for the error. More specifically, we consider Chebyshev polynomials, Clenshaw-Curtis procedures and product formulas. Estimates for the employed degrees of approximation are available in the theory of approximation, and these estimates can be supported or refined by numerical computation.

Error detecting system

Abstract: A method and apparatus for storing data in which the data is checked for an error without requiring the data to include an error correction code. Included in the system is a logic circuit for dividing a data word by a polynomial during the time the data word is being written into the primary memory unit resulting in the generation of a remainder which is stored in an auxiliary memory unit. When reading the data word from the primary memory unit, the data word is again divided by the same polynomial and the remainder compared with the remainder stored in the auxiliary memory unit. If the remainders match, no error was introduced during the storing of the data in the main memory unit. If the remainders do not match, an error is indicated. This system allows a data word to be stored in a main or primary memory unit without requiring the word to include error correction bytes.

Investigation of second order properties of statistical estimators in a scheme of independent observations

Abstract: The author obtains asymptotic expansions of statistical estimators, their moments, the integral risk, etc., with an investigation of the remainder terms of the expansions. Bibliography: 25 titles.

Matrix representation and estimations of remainder term of many-knot spline interpolating curves and surfaces

Abstract: Many-knot spline interpolation is a new class of curve and surface fitting method,created by the author in 1974. Many-knot spline is suitable to Computer Aided Geo-metrie Design and handling problems for some data. In this paper the matrix forms of representation of interpolating function are con-sidered, the estimations of remainder term for quadratic and cubic many-knot splineare given: ||R_2~((l))(x)|| = O(h~(3--1)), l = 0, 1, 2and ||R_3~((l))(x)|| = O(h~(4--1)), l = 0, 1, 2, 3.

Numbers and Geometry

Abstract: In Parts I and II we have gone out of our way to stress the enormous difference between the finite procedures of ordinary arithmetic, and those mathematical concepts whose very meaning depends on the introduction and interpretation of infinite processes. In contrast, you have in the past been encouraged to use real numbers (whether rational or irrational) in a naive, unquestioning way—especially in geometry: for example, you have been quietly encouraged to assume that, if we measure the length of a line segment AB in terms of some given unit segment CD, then its length AB/CD can obviously be expressed as a real number. While this is obvious when CD fits into AB a whole number of times leaving no remainder, or when CD and AB have some common measure MN which fits into CD precisely b times with no remainder and into AB precisely a times with no remainder (in which case AB/CD = a/b), it is not at all obvious in general. In Chapter 11.13 we saw one way of justifying the belief that AB can always be measured in terms of CD, but it was not exactly obvious!

Representation of integers by positive ternary quadratic forms (a new modification of the discrete ergodic method)

Abstract: One gives a detailed presentation of a new modification of the discrete ergodic method outlined in A. V. Malyshev's note (this “Zapiski,”50, 179–186 (1975)). One gives new proofs for the asymptotic formulas obtained in Chap VI of A. V. Malyshev's monography (Tr. Mat. Inst. Akad. Nauk SSSR,65 (1962). One obtains estimates for the remainder terms of this formulas under the assumption of some hypotheses about the zeros of Dirichlet's L -functions.

Multiplaying and dividing circuits

Abstract: PURPOSE:To execute an operation of multiplication and division, which is low in power consumption and high in speed, by constituting a unit circuit of a C-MOS gate, constituting a division carrying circuit of an E/D type MOS gate, and reducing the number of elements and a chip area. CONSTITUTION:Binary numbers P0, P1-P7 of 8 bits are multiplied by binary numbers B0, B1-B7 of same 8 bits, binary numbers S0, S1-S15 of 16 bits, being said multiplied value are derived, or binary numbers A0, A1-A14 of 15 bits are divided by binary numbers B0, B1-B7 of 8 bits, and the quotient shown by binary numbers Q0, Q1-Q7 of 8 bits, being said divided result, and the remainder shown by binary numbers S0, S1-S15 of 16 bits are derived. These operations are selectively designated by a control signal. In this way, when a unit circuit is constituted of a CMOS gate, and a division carrying circuit is constituted of an E/D type MOS gate, a chip area is reduced, and the processing of multiplication and division, which is low in power consuption and high in speed is executed.

Spaces for which the generalized Cantor space 2^{} is a remainder

Abstract: Let X" be a locally compact noncompact space, m be an infinite cardinal and | J | = m. Let F( X) be the algebra of continuous functions from X into R which have finite range outside of an open set with compact closure and let /( X) = {g G F(X): g vanishes outside of an open set with compact closure}. Conditions on R(X) = F(X)/I(X) and internal conditions are obtained which characterize when X has 2J as a remainder. 1. Introduction. Throughout this paper all spaces are assumed to be completely regular and Hausdorff. We let LC denote the class of all locally compact and noncompact spaces. A compactification of a space A" is a compact space which contains A" as a dense subspace and a remainder of X is any aX \ X where aX is a compactification of X. If aX and bX are two compactifications of X, then aX *£ bX if there is a continuous function g: aX -» bX such that g(x) = x for each x G X. For a set A let | A | denote the cardinality of A. Recently Hatzenbuhler and Mattson (HM) have obtained an internal characteriza- tion which characterizes when a given space X G LC has every compact metric space as a remainder. The condition given by them assures that if X satisfies this condition

A method of calculating the field of a point source in a waveguide

Abstract: In the paper a representation is obtained of the field of a point source in a waveguide with quadratic dependence of the index of refraction in the form of a sum of normal, geometrical-optics waves and a remainder. Sufficient conditions on the number of separate normal and geometrical-optics waves are found. The remainder is expressed by a simple formula.

Detector for multiplication error

Abstract: PURPOSE:To reduce a load on a circuit and to increase an arithmetic speed by generating a remainder Pn, a remainder B, a remainder An+An-1, and a remainder Pn-2 for the detection of a multiplication error, by calculating PnV. B.X(An+An-1)+(Pn-2), and by performing the remainder calculation in every two-loop back cycle. CONSTITUTION:If a partial multiplier An is stored in a partial remainder register 3 in the 2nd loop back cycle and a remainder generator 4 generates a remainder multiple, the contents of a register 5 and this remainder multiplier are transferred to an adder 6 and a multiplier 7 to perform multiplication, and the result is transferred to an adder 9. A multiplication result, on the other hand, is outputted from a multiplying circuit 21 and then transferred from a register 12 to the adder 9 through a remainder generator 10 to be transferred to a comparator 13. When coincidence is not obtained, an error signal is generated, and prescribed following processing is performed.

Cyclic redundancy check operating circuit

Abstract: PURPOSE:To execute a CRC operation of a byte unit in bit parallel, by providing an exclusive ''or'' gate of an input data and an old remainder of CRC, a feedback value generating circuit, and a logical circuit for generating a new remainder. CONSTITUTION:Parallel input data D1-D8 of 8 bits are made to take an exclusive ''or'' with 8 bits of the low rank side of an output signal (b) of a remainder register 101, at every corresponding bit, in a logical gate 102, are outputted as a parallel signal (c) of 8 bits, and are inputted to a feedback value generating circuit 103. The circuit 103 generates feedback values F1-F8 (d) corresponding to the input pattern, and inputs it to a logical circuit 104. The circuit 104 executes a prescribed operation by 8 bits of the high rank side of the register 101, and the signal (d), and new remainders R1-R16 (e) are generated. The new remainder (e) is fed back to the register 101, is written in the register 101 by a write clock W-CLK, and one CRC operation is completed.

A technique for evaluating sums by means of complex integration

Abstract: We derive a new technique for evaluating or approximating sums by means of complex integration. Our result is sufficiently general that it is applicable to a wide variety of functions. We consider examples that illustrate the power of the technique: our first example is an alternative derivation of the Euler–Maclaurin sum formula for the case in which the remainder term vanishes, and our other two examples show how our technique can be applied when the Euler–Maclaurin formula is not useful.

A remainder formula and limits of cardinal spline interpolants

Abstract: A Peano-type remainder formula f(x) S, J(f; x) = f c. K,( (x, t)f (n+ 1)(t) dt for a class of symmetric cardinal interpolation problems C.I.P. (E, F, x) is obtained, from which we deduce the estimate 1lfSn,r(f; )I I K I I(n+ ) 1o It is found that the best constant K is obtained when x comprises the zeros of the EulerChebyshev spline function. The remainder formula is also used to study the convergence of spline interpolants for a class of entire functions of exponential type and a class of almost periodic functions.