Showing papers on "Residue number system published in 2015"
TL;DR: The aim in this paper is to show this revolution by discussing interesting development in RNS and foster the innovative use of RNS for more applications by investigating how this unconventional number system can be leveraged to benefit their implementation.
Abstract: Residue Number System (RNS) is a non-weighted number system which was proposed by Garner back in 1959 to achieve fast implementation of addition, subtraction and multiplication operations in special-purpose computations. Unfortunately, RNS did not turn out as a popular alternative to two?s complement number system in those days. The rigidity of instruction set architectures of the market-dominant computers and microprocessors then has been the main barrier to sustain the development of RNS-based applications. In recent years, technological advancement in semiconductor technology has revived the interests to reconsider RNS for application-specific computing. There are at least two unique motivations which make RNS computations more attractive and applicable in modern digital signal processing applications. Firstly, the modular and distributive properties of RNS are used to achieve performance improvements especially in the emerging distributed and ubiquitous computing platforms such as cloud, wireless ad hoc networks, and applications which require tolerance against soft error. Secondly, energy efficiency becomes a key driver in the continual densification of complementary metal oxide semiconductor (CMOS) digital integrated circuits. The high degree of computational parallelism in RNS offers new degree of freedom to optimize energy performance, particularly for very long word length arithmetic such as those involved in the hardware implementation of cryptographic algorithms. Our aim in this paper is to show this revolution by discussing interesting development in RNS and foster the innovative use of RNS for more applications. Different applications of RNS are investigated to demonstrate how this unconventional number system can be leveraged to benefit their implementation.
111 citations
01 Sep 2015
TL;DR: The nested RNS (NRNS), which recursively decomposes the RNS, can decompose the MAC unit into circuits with small sizes and lead to a balanced usage of FPGA resources leads to a high clock frequency with less hardware.
Abstract: A pre-trained deep convolutional neural network (DCNN) is the feed-forward computation perspective which is widely used for the embedded vision systems. In the DCNN, the 2D convolutional operation occupies more than 90% of the computation time. Since the 2D convolutional operation performs massive multiply-accumulation (MAC) operations, conventional realizations could not implement a fully parallel DCNN. The RNS decomposes an integer into a tuple of L integers by residues of moduli set. Since no pair of modulus have a common factor with any other, the conventional RNS decomposes the MAC unit into circuits with different sizes. It means that the RNS could not utilize resources of an FPGA with uniform size. In this paper, we propose the nested RNS (NRNS), which recursively decompose the RNS. It can decompose the MAC unit into circuits with small sizes. In the DCNN using the NRNS, a 48-bit MAC unit is decomposed into 4-bit ones realized by look-up tables of the FPGA. In the system, we also use binary to NRNS converters and NRNS to binary converters. The binary to NRNS converter is realized by on-chip BRAMs, while the NRNS to binary one is realized by DSP blocks and BRAMs. Thus, a balanced usage of FPGA resources leads to a high clock frequency with less hardware. The ImageNet DCNN using the NRNS is implemented on a Xilinx Virtex VC707 evaluation board. As for the performance per area GOPS (Giga operations per second) per a slice, the proposed one is 5.86 times better than the existing best realization.
49 citations
TL;DR: The largest dynamic range within which any two nonnegative integers can be uniquely determined from their residues modulo a set of moduli is determined.
Abstract: In this letter we determine the largest dynamic range within which any two nonnegative integers can be uniquely determined from their residues modulo a set of moduli. We also propose an efficient determination algorithm that extends a recent known result.
28 citations
TL;DR: Modified correction codes – based on Residue Number System – are proposed to improve the data transmission robustness in WSN.
Abstract: The WSN standard IEEE802.15.4 basically uses the unlicensed frequency of 2,4 GHz for data transmission in a variety of devices, standards and applications: IEEE802.11, Bluetooth and etc. In this paper we proposed modified correction codes – based on Residue Number System – to improve the data transmission robustness in WSN. These codes are characterized by high correction characteristics as well as the simplified coding procedure. There are given examples, and circuits of the both coder and decoder are designed for such modified correction codes using the Residue Number System and CPLD. DOI: http://dx.doi.org/10.5755/j01.eee.21.1.6657
27 citations
TL;DR: Experimental results presented in this paper shows that the watermark can be successfully embedded and extracted from an image, without distorting the original image using the proposed technique.
Abstract: Information hiding or data hiding, also known as watermarking, has become a part and parcel of covert communication and copyright protection. Maximizing watermark payload is a major challenge for watermark researchers. To overcome this issue, we have proposed a new color image watermarking technique, using residue number system (RNS). RNS refers to a large integer using a set of smaller integers which relies on the Chinese remainder theorem of modular arithmetic for its operation. The proposed method takes pixel values from three watermark images and embeds them into the main cover image. Experimental results presented in this paper shows that the watermark can be successfully embedded and extracted from an image, without distorting the original image using the proposed technique. The high peak signal to noise ratio (PSNR) and payload values claims the robustness of the proposed method.
20 citations
22 Jun 2015
TL;DR: This paper presents an RNS algorithm resolving the Closest Vector Problem (CVP), which is particularly efficient for a certain class of lattice basis and an optimized Cox-Rower architecture adapted to the proposed algorithm.
Abstract: Residue Number Systems (RNS) are naturally considered as an interesting candidate to provide efficient arithmetic for implementations of cryptosystems such as RSA, ECC (Elliptic Curve Cryptography), pairings, etc. More recently, RNS have been used to accelerate fully homomorphic encryption as lattice-based cryptogaphy. In this paper, we present an RNS algorithm resolving the Closest Vector Problem (CVP). This algorithm is particularly efficient for a certain class of lattice basis. It provides a full RNS Babai round-off procedure without any costly conversion into alternative positional number system such as Mixed Radix System (MRS). An optimized Cox-Rower architecture adapted to the proposed algorithm is also presented. The main modifications reside in the Rower unit whose feature is to use only one multiplier. This allows to free two out of three multipliers from the Rower unit by reusing the same one with an overhead of 3 more cycles per inner reduction. An analysis of feasibility of implementation within FPGA is also given.
20 citations
18 citations
TL;DR: According to the results, any implementation involving the diagonal function proposed to date results in excessive hardware overhead and delay, which make it impractical from the application point of view, so that it cannot compete with more traditional approaches.
15 citations
Patent•
03 Jun 2015
TL;DR: In one or more implementations, an RNS ALU or processor comprises a plurality of digit slices configured to perform modular arithmetic functions as discussed by the authors, and operation of the digit slices may be controlled by a controller.
Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations. In one or more embodiments, an RNS ALU or processor comprises a plurality of digit slices configured to perform modular arithmetic functions. Operation of the digit slices may be controlled by a controller. Residue numbers may be converted to and from fixed or mixed radix number systems for internal use and for use in various computing systems.
15 citations
22 Jun 2015
TL;DR: This paper investigates the following three problems of logical gates count reduction when two different bases share the same hardware modules and proposes algorithmic answers to some of the questions that may face a designer when implementing RNS solution.
Abstract: Residue Number System (RNS) is nowadays considered as a real alternative to other hardware architectures for handling large-number computations In this paper we propose algorithmic answers to some of the questions that may face a designer when implementing such solution More precisely, we investigated the following three problems First, we propose an efficient method for constructing maximal bases noticing that this problem can be seen as a max-clique problem Second we consider the logical gates count reduction when two different bases share the same hardware modules Again it is linked to graph theory since it corresponds to finding a maximum weighted matching Eventually we detail how the presence of DSP blocks in FPGAs can be leveraged to reach higher design frequencies by implementing full computation units inside
9 citations
TL;DR: Experimental results show that the proposed algorithm can encrypt and decrypt text without loss of inherent information and faster than the state of the art, and offers firm resistance to Brute-force and key sensitivity attacks.
Abstract: In this paper, we present an algorithm for Residue Number System (RNS) implementation of RSA cryptography based on an existing RNS division algorithm. The proposed algorithm and that of the state of the art were written in C++ programming language to compare their efficiency with respect to execution time. Experimental results show that our algorithm can encrypt and decrypt text without loss of inherent information and faster than the state of the art. It also offers firm resistance to Brute-force and key sensitivity attacks. Considering the moduli-set {2, 3, 5} experimental results shows that, our proposed algorithm is 7.29% and 15.51%, faster than the state of the art algorithm for integer and non-integer quotients respectively. Also, for the moduliset {7, 9, 11}, our algorithm is as well 11.29% and 10.36% faster than that of the state of the art algorithm for integer and non-integer quotient respectively. We carried out an error analysis of the experimental results at 95 degrees significance level.
01 Dec 2015
TL;DR: The proposed SAD architecture is based on a very recent advance in fast sign-detection algorithms for RNS, and the experimental results show that the proposed architecture has higher speed and less area than previous SAD implementations.
Abstract: The Sum of Absolute Differences (SAD) is widely used in motion-estimation algorithms, the most computationally intensive task in video compression, and also in determining similarities between two data sets. This paper proposes a SAD hardware implementation using a Residue Number System (RNS). Residue Number Systems have been used for decades in designing low-power and high-speed computer hardware, because of their inherent parallel structure. In RNS, large integers are represented as sets of smaller integers or residues, where the number bases or moduli are mutually prime. Since these residues are independent from each other, mathematical operations such as addition, subtraction and multiplication can be carried out without any carry propagation between residues, which is in most cases a limiting factor in binary systems. However, some arithmetical operations such as comparison and division are more difficult in RNS than in conventional binary systems, such as determining the sign and magnitude comparison of two numbers. The proposed SAD architecture is based on a very recent advance in fast sign-detection algorithms for RNS, and the experimental results show that the proposed architecture has higher speed and less area than previous SAD implementations.
29 Jun 2015
TL;DR: This paper proposes a variant of the LRA in RNS: to change only one or a few moduli of the RNS basis, which reduces the cost of the randomization and makes it possible to be executed at each loop of a modular exponentiation.
Abstract: On an embedded device, an implementation of cryptographic operation, like an RSA modular exponentiation [12], can be attacked by side channel analysis. In particular, recent improvements on horizontal power analysis [3, 10] render ineffective the usual counter-measures which randomize the data at the very beginning of the computations [2, 4]. To counteract horizontal analysis it is necessary to randomize the computations all along the exponentiation. The leak resistant arithmetic (LRA) proposed in [1] implements modular arithmetic in residue number system (RNS) and randomizes the computations by randomly changing the RNS bases. We propose in this paper a variant of the LRA in RNS: we propose to change only one or a few moduli of the RNS basis. This reduces the cost of the randomization and makes it possible to be executed at each loop of a modular exponentiation.
28 Sep 2015
TL;DR: A single error correction algorithm based on Redundant Residue Number System (RRNS) in communication systems is discussed and the practical feasibility of this algorithm is analyzed in terms of Bit Error Rate (BER).
Abstract: Communication channel is highly prone to noise and therefore error correcting codes are required to protect the transmitted data. Residue Number System (RNS) is defined as the representation of an integer in the residue field. Redundant Residue Number System (RRNS) is obtained by adding some redundant residues in the RNS. In RNS, the arithmetic operations are carry free, so errors do not propagate from one residue to other. This enables RRNS to give a promising way to provide a very fast arithmetic in the field of digital computers. The potentiality of the fast RRNS based arithmetic has not yet been explored in communication systems. This paper discusses a single error correction algorithm based on Redundant Residue Number System (RRNS) in communication systems. The practical feasibility of this algorithm is analyzed in terms of Bit Error Rate (BER). The Bit Error Rate (BER) performance of RRNS codes with error correction algorithm for M-ary modulation in an AWGN channel is analyzed and is compared with conventional single bit error correction code, Hamming code. The simulation results show that RRNS codes outperforms Hamming codes in terms of BER.
01 Dec 2015
TL;DR: In this article, the use of residue number system (RNS) for pseudo-noise (PN) sequence generation has been investigated and compared with other PN sequences such as m-sequence and Gold sequence.
Abstract: Pseudo-noise (PN) sequences are sequences that are practically deterministic but passes many test for randomness. PN sequences are used in the CDMA systems for the detection of received data which is affected by multiple access interference (MAI). The sequences with low cross correlation factor performs better in the presence of interference. This article presents the generation of PN sequence using residue arithmetic. Residue number system (RNS) is a non-weighted, non-positional carry free arithmetic which represents an integer as a set of remainders. The use of RNS in PN sequence generation offers low cross correlation values. This property is investigated in this article and is compared with other PN sequences such as m-sequence and Gold sequence. Simulation results shows that the performance of RNS based PN sequence is superior than other sequences.
TL;DR: The proposed method is able to detect overflow in RNS addition without full reverse conversion and prevents the representation of wrong numbers as a result of overflow, thus the scheme gives the accurate result without errors whether overflow occurs or not.
Abstract: In this paper, an efficient scheme for detecting and correcting overflow during addition in Residue Number System (RNS) is presented. The approach which is novel to the moduli set 2 − 1, 2 , 2 + 1 is based on the Chinese Remainder Theorem and demonstrates theoretically to be a very fast scheme compared to similar state of the art schemes. The proposed method is able to detect overflow in RNS addition without full reverse conversion; Additionally, the scheme also prevents the representation of wrong numbers as a result of overflow, thus the scheme gives the accurate result without errors whether overflow occurs or not. A comparison, which proves the efficiency of the proposed scheme, in terms of delay and area requirements is also presented. General Terms Residue Number System, Circuits and Systems, Computer Arithmetic, Computer Architecture, Overflow, Digital Signal Processing.
31 Aug 2015
TL;DR: This paper deals with a new technique of multiple-precision computations, based on the use of modular-positional floating-point format for representation of numbers, thus enabling high-speed processing of the significands with possible parallelization by RNS modules.
Abstract: Floating-point machine precision is often not sufficient to correctly solve large scientific and engineering problems Moreover, computation time is a critical parameter here Therefore, any research aimed at developing high-speed methods for multiple-precision arithmetic is of great immediate interest This paper deals with a new technique of multiple-precision computations, based on the use of modular-positional floating-point format for representation of numbers In this format, the significands are represented in residue number system RNS, thus enabling high-speed processing of the significands with possible parallelization by RNS modules Number exponents and signs are represented in the binary number system The interval-positional characteristic method is used to increase the speed of executing complex non-modular operations in RNS Algorithms for rounding off and aligning the exponents of numbers in modular-positional format are presented The structure and features of a new multiple-precision library are given Some results of an experimental study on the efficiency of this library are also presented
TL;DR: Modeling these developments on Xilinx Kintex 7 FPGA showed that the proposed methods of decrease computational complexity of determining signs and comparing numbers in the RNS compared to that in well-known architectures based on the Chinese remainder theorem with generalized positional notation.
Abstract: New algorithms for determining the sign of a modular number and comparing numbers in a residue number system (RNS) have been developed using the Chinese remainder theorem with fractional values. These algorithms are based on calculations of approximate values of fractional values determined by moduli of the system. Instrumental implementations of the new algorithms are proposed and examples of their applications are given. Modeling these developments on Xilinx Kintex 7 FPGA showed that the proposed methods of decrease computational complexity of determining signs and comparing numbers in the RNS compared to that in well-known architectures based on the Chinese remainder theorem with generalized positional notation.
TL;DR: The notion of base transformation to complement residue scaling in reducing the overall arithmetic processing costs of multi-base RNS is introduced and results show that its VLSI implementation efficiency outperforms the best possible improvised solution and the approach of removing one modulus channel.
Abstract: Many RNS-based implementations of digital signal processing algorithms have experienced the overkill of arithmetic operator sizes due to the choice of moduli set to accommodate for the occasional high precision operations. As the sizes of modulo arithmetic operators are fixed by the choice of their moduli, they are not scalable even if there is a subsequent reduction in the dynamic range. This paper introduces the notion of base transformation to complement residue scaling in reducing the overall arithmetic processing costs of multi-base RNS. A new algorithm is proposed to directly map the residues of signed integers from one modulo-arithmetic friendly base $S_{1}\equiv\{2^{n}-1, 2^{n+k}, 2^{n}+1\}$ to another $S_{2}\equiv\{2^{n-\alpha}-1, 2^{n+k-\alpha}, 2^{n-\alpha}+1\}$ , to reduce the word lengths of residue arithmetic operators by $\alpha$ bits along with the reduction of dynamic range. It infers the quantized segment in $S_{2}$ directly from the quantized segment of the input residues in $S_{1}$ to avoid the complex reverse conversion and sign detection operations. Our synthesis results show that its VLSI implementation efficiency, in terms of area-delay product and energy consumption, outperforms the best possible improvised solution and the approach of removing one modulus channel. Noticeably, the improvements enhance with increasing $\alpha$ .
22 Jun 2015
TL;DR: New designs of efficient parallel prefix modular adders are proposed with new designs with (5 + 2 log n)△G latency without any penalty in area consumption or power dissipation.
Abstract: The residue number system t = {2n -- 1, 2n, 2n + 1} has been extensively studied towards perfection in realization of efficient parallel prefix modular adders, with (3 + 2log n ?G) latency. Many applications, such as digital signal processing require fast modular operations. However, relying only on t limits the magnitude of n, and accordingly the dynamic range. Therefore, additional mutually prime moduli are required to accommodate for wider dynamic range. On the other hand, speed of modular arithmetic operations for the additional moduli should be as close as possible to those in t. This could be best met by the moduli of the form 2n -- (2q + 1), with 1 ale; q ale; n -- 2, such as 2n -- 3, 2n -- 5. However, the fastest parallel prefix realization of modulo-(2n -- 2q -- 1) adders that we have encountered in the relevant literature, claims (7 + 2 log n)?G latency. Motivated by the need to reduce the latter, we propose new designs of such adders with (5 + 2 log n)?G latency without any penalty in area consumption or power dissipation. The proposed modular addition algorithm entails supplementary representation of residues in [0,2q], as [2n -- (2q + 1), 2n -- 1]. This leads to additional performance efficiency similar to the effect of double zero representation in modulo-(2n -- 1) adders. The aforementioned analytically evaluated speed gain and improvements in other figures of merit are also supported via circuit simulation and synthesis.
01 Oct 2015
TL;DR: This paper proposes a novel RRNS which uses high-radix signed-digit (HRSD) encoding which is called HRSD-RNS, and proposes an efficient adder for HRSDs, and demonstrates how the proposed representation can be utilized to derive a unified design for the moduli set, which opens the possibility to design reliable RRNS processors with low hardware redundancy.
Abstract: Carry propagation is a main problem in Residue Number System (RNS) arithmetic. This overhead can be eliminated by using redundant number representation which results in Redundant Residue Number System (RRNS). The RRNS which uses Signed-Digit (SD) encoding (SD-RNS) has been shown as an efficient number system. However, SD-RNS cannot provide flexible trade-off between area and speed. To solve this problem, we first propose a novel RRNS in this paper, which uses high-radix signed-digit (HRSD) encoding which is called HRSD-RNS. Then, we propose an efficient adder for HRSD-RNS. The results indicate that the HRSD-RNS modulo 2n−1 and modulo 2n+1 adders outperform power and power-delay-product (PDP) of the existing RRNS adders. Moreover, we demonstrate how the proposed representation can be utilized to derive a unified design for the moduli set {2n−1, 2n, 2n+1}, which opens the possibility to design reliable RRNS processors with low hardware redundancy. In addition, the proposed structure can be employed in conjunction with any fast state of the art HRSD adder without requiring any extra hardware for modular addition.
10 Jul 2015
TL;DR: This paper presents a single bit error correction algorithm using Redundant Residue Number System (RRNS), which doesn't require table lookup which helps to save memory during implementation.
Abstract: In Residue Number System (RNS), a large integer is represented as a set of smaller integers called residues. Redundant Residue Number System (RRNS) is obtained by adding some redundant residues which brings in error detection and error correction capability. This capability makes RRNS a promising way to provide a very fast arithmetic in the field of digital computers. At the receiver, RRNS codes are decoded using Chinese Remainder theorem (CRT). An alternative scheme called Mixed Radix Conversion (MRC) is also used which results in low decoding complexity when compared to CRT. This paper presents a single bit error correction algorithm using RRNS. This algorithm doesn't require table lookup which helps to save memory during implementation. Representative examples are given.
01 Dec 2015
TL;DR: The primary advantage of the methods is that the conversions and arithmetic operations utilize the modulo m SD adders (MSDAs) only and the proposed basic circuits have high speed structures in a constant delay time.
Abstract: In this paper, high-speed Signed-Digit (SD) architectures of binary-to-residue and residue-to-binary conversions for residue number system (RNS) with the moduli set (2n, 2n − 1, 2n + 1) are proposed. The complexity of the conversions and residue arithmetic operations has been greatly reduced by using compact forms for the multiplicative inverse and the fast residur SD addition algorithm. The relationships of the proposed binary-to-residue and residue-to-binary conversions using the residue SD numbers result in simpler hardware requirements for the converters. The primary advantage of our methods is that our conversions and arithmetic operations utilize the modulo m SD adders (MSDAs) only and the proposed basic circuits have high speed structures in a constant delay time.
Journal Article•
TL;DR: In this article, an efficient sum of absolute difference (SAD) tree and its hardware architecture have proposed in Residue Number System (RNS) based moduli and implements the full search variable block size motion estimation (FSVBSME).
Abstract: For better video quality in the H.264/AVC video coding technology, motion estimation has massive growth due to improvements in searching algorithms and improved significantly in compression efficiency and complexity, specifically in area, power and throughput. In this paper, an efficient sum of absolute difference (SAD) tree and its hardware architecture have proposed in Residue Number System (RNS) based moduli and implements the full search variable block size motion estimation (FSVBSME). The main advantage is that for performing carry free addition operation, residue number system is being considered as a non weighted number system to binary number system, RNS is mostly suitable for image…
21 Apr 2015
TL;DR: This work presents an algorithm that results in very good moduli set for the given requirements of Residue Number System, and proves the efficiency of it.
Abstract: Heterogeneous architectures require custom intellectual property (IP) blocks, named ‘accelerators’, that perform an operation efficiently Residue Number System (RNS), a non binary compatible arithmetic system, can be used in such accelerators One fundamental challenge in the design of RNS circuits is the selection of the moduli set Here, we present our algorithm that results in very good moduli set for the given requirements Experimental results and comparisons with similar algorithms, prove the efficiency of it The algorithm has been implemented into a public web tool and is available via a web browser
01 May 2015
TL;DR: A new novel five moduli set for even n with its forward conversion circuits are proposed, which have a dynamic range that can represent up to 5n - 1 bits while keeping the moduli small enough and the converters efficient.
Abstract: Choosing a proper moduli set for Residue Number System based building blocks greatly affects the performance of the whole system. The prevalent issue is that as the number of moduli increases the speed of the residue arithmetic units increases, whereas the forward converters (Binary to Residue converters) and Reverse converters (Residue to Binary converters) become slower and more complex. Different moduli sets with efficient converter are proposed by researchers. One of the most well formed special moduli set is {2n -- 1, 2n, 2n + 1}. However some applications like cryptography algorithms require a very large dynamic range which cannot be achieved efficiently using the special moduli sets that consists of three or four moduli. When the required dynamic range is very large, these moduli have to be large, which results in lower performance of the arithmetic units in each modulo channel. In that case, the best solution is to use many small moduli (five or more) to represent the large dynamic range efficiently. In this paper a new novel five moduli set {2n -- 1, 2n, 2n + 1, 2n+1 -- 1, 2n -- 1 -- 1} for even n with its forward conversion circuits are proposed. The proposed moduli set have a dynamic range that can represent up to 5n -- 1 bits while keeping the moduli small enough and the converters efficient.
01 Dec 2015
TL;DR: The simulation results show that RRNS codes have around 3dB better error rate performance than RS codes at a Symbol Error Rate (SER) of 10-3.
Abstract: Error detection and correction techniques are used to accomplish reliable data transmission through a communication channel. Redundant Residue Number System (RRNS) is a type of number system in which the arithmetic operations are carry free, so errors do not propagate from one residue to other. This paper analyses the performance of burst error correction algorithm using RRNS code and is compared with a conventional burst error correction technique, Reed-Solomon (RS) code in terms of Symbol Error Rate (SER) in an AWGN channel as well as Rayleigh fading channel. The simulation results show that RRNS codes have around 3dB better error rate performance than RS codes at a SER of 10−3. Simulations and performance comparisons are done using MATLAB®.
TL;DR: The analysis of the performance of the proposed modulator on above mentioned number systems indicates the superiority of other number systems over binary number system.
Abstract: This paper presents a comparative study of the performances of arithmetic units, based on different number systems like Residue Number System (RNS), Double Base Number System (DBNS), Triple Base Number System (TBNS) and Mixed Number System (MNS) for DSP applications. The performance analysis is carried out in terms of the hardware utilization, timing complexity and efficiency. The arithmetic units based on these number systems were employed in designing various modulation schemes like Binary Frequency Shift Keying (BFSK) modulator/demodulator. The analysis of the performance of the proposed modulator on above mentioned number systems indicates the superiority of other number systems over binary number system.
28 Nov 2015
TL;DR: A design method is proposed on the basis of residue number system (RNS), which has been considered as an important methodology of high-speed computation to accelerate the FIR filtering process.
Abstract: Finite impulse response (FIR) filters implemented in binary weighted number system suffer from the carry propagation delay. To accelerate the FIR filtering process, a design method is proposed on the basis of residue number system (RNS), which has been considered as an important methodology of high-speed computation. The arithmetic operations are decomposed into a set of small modular operations, which can be performed by several sub-filters in parallel. At the end of filtering, the residue signals are converted to conventional binary notation via Chinese remainder theorem. The performance of the presented RNS FIR filter is evaluated by computer simulation. The results show that frequency specifications are satisfied and the time delay of arithmetic operations is substantially shortened.