Showing papers on "Serial port published in 2003"

Communication interface system for locally analyzing computers

Abstract: A communication interface system including a computer and a handheld device that communicate with each other via respective communication ports. The computer communication port is a serial port or an infrared transceivers conveniently located on the front bezel of the computer. In serial embodiments, the computer executes the appropriate driver and interface applications to enable transfer of information to the handheld device. In infrared embodiments, the computer includes a microcontroller, an I2C bus and memory, where the microcontroller implements infrared communication protocol. Alternatively, the computer may further include a management processor that either replaces or cooperates with the microcontroller. Auxiliary power may enable handheld communications when the computer is shut down. The handheld device interfaces with the computer communication port to retrieve and display the status information. The handheld device effectively replaces external LCD health status hardware that typically consumes valuable space on the front bezel of the computer. The handheld device may further replace traditional input/output (I/O) devices, such as a keyboard, a mouse, a monitor, a disk drive, etc. For example, the handheld device may be utilized to monitor and control boot up operations of the computer, such as displaying boot up information or otherwise executing setup or, diagnostic routines.

Optical transceiver module with multipurpose internal serial bus

Abstract: The optical transceiver module includes an optical transmitter and an optical receiver. The optical transceiver module also includes an internal serial bus and a plurality of addressable components electrically coupled to the internal serial bus. Each of the addressable components included a serial interface for communicating with the internal serial bus, and a memory. Each addressable component also includes a unique address or chip select logic coupled to a controller via a chip select line. This allows data to be addressed to specific addressable components. The addressable components may include a laser driver, a laser bias controller, a power controller, a pre-amplifier, a post-amplifier, a laser wavelength controller, a main controller, a electrothermal cooler, an analog-to-digital converter, a digital-to analog converter, an APD bias controller, or any combination of the aforementioned components.

High speed serial interface test

Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface The pseudo-random sequence is then descrambled and compared to the input word Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment

High-speed data transmission device

Abstract: A high-speed data transmission device is provided. The high-speed data transmission device comprises a controller for converting a data complaint with a serial port interface into a data complaint with a parallel port interface, a controller for converting a data complaint with a parallel port interface for transmitting into a Flash RAM like memory storage element. The controller that converts the data complaint with the parallel port interface for transmitting into a Flash RAM like memory storage element is controlled by the controller for converting the data complaint with the serial port interface into the data complaint with the parallel port interface.

Bluetooth serial adapters

Abstract: A Bluetooth serial adapter comprising a Bluetooth connection module (21) for conducting Bluetooth communication with another Bluetooth enabled device, a serial connector SP allowing connection of a serial cable between the adapter and a device having a serial port, and a serial to Bluetooth interface (23) arranged for: receiving serial connection control commands input via the serial connector; mapping received serial connection control commands to Bluetooth connection control events; and outputting the so determined Bluetooth connection control events to the Bluetooth connection module. The interface (23) may be implemented by making use of a virtual machine provided on the Bluetooth chip.

Embedded Ethernet and Internet Complete

Abstract: From the Publisher: Bringing together two areas of computer technology-networking and embedded systems-this developer's guide offers guidance and examples for each of these, with a focus on the special requirements and limits of embedded systems. Because developing an embedded system for networking requires knowledge from many areas, including circuit design, programming, network architecture, and Ethernet and Internet protocols, developers are given valuable technical information on each that can be put to use right away. Covered are the advantages and limits of using Ethernet to connect embedded systems in a local network, hardware and program code needed to connect an embedded system to an Ethernet network and the Internet, and how to build a network. Also discussed are how embedded systems can use TCP/IP and related protocols and how personal-computer applications can use the protocols to communicate with embedded systems. Developers will learn how their Web server's pages can include dynamic, real-time content and respond to user input. Author Biography: Jan Axelson has written dozens of articles for technical publications including Embedded Systems Programming, EDN, and Circuit Cellar. She is the author of USB Complete, Serial Port Complete, and Parallel Port Complete. She lives in Madison, Wisconsin.

Multi-rate, multi-port, gigabit SERDES transceiver

Abstract: A multi-port Serdes transceiver (400) includes multiple parallel ports (102) and serial ports (104) and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip (400) can connect any one of serial ports (104) to another serial port or to one of the parallel ports (102). The substrate layout of the multi-port Serdes transceiver chip (400) is configured so that the parallel ports (102) and the serial ports (104) are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus (106) can be described as a 'ring' structure (or donut 'structure') around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.

Serially connectable USB drive

Abstract: The present invention relates to a serially connectable USB drive. The USB drive has an upstream and a downstream port to facilitate the serial connection of other USB drives or the networking of other USB peripheral devices. The USB drive is equipped with a switch circuit. In the case that another serially connectable USB drive or a standard USB drive is inserted into the downstream port, the switch circuit executes the serial connection controlling function and connects the memories of both USB drives. In the case that a standard USB peripheral device is inserted, the switch circuit changes figuration into a USB HUB for the memories of USB drive and the USB peripheral device to communicate respectively with the computer mainframe or other microprocessor units.

Controller design for a wearable, near-field haptic display

Abstract: In this paper, we address the problem of providing near-field haptic feedback in a wearable, scalable manner. Our solution, called the TactaBoard, supports the independent control of 16 outputs on a single controller board using a standard serial port. We have tested the system with several types of output devices, including low-cost pager motors and fans. Based on pulse-width modulation, the system can generate an output frequency from 0.3 Hz to 316 Hz. We provide a detailed description of the characteristics of our system, and present early results from empirical studies we have conducted with one possible configuration of tactors. Future enhancements to the TactaBoard system include the ability to daisy chain multiple boards on one control bus, and support for other classes of output devices such as those requiring an H-Bridge. Finally, we present some possible applications where this type of system might be useful.

Systems for acquiring data from a facility and method

Abstract: A field instrument and system for obtaining pressure, flow and temperature data from a facility The field instrument includes an enclosure having an opening therein An integrated analog sensor is sealingly contained within the opening The field instrument further contains an external analog sensor An analog to digital converter converts the analog signals to digital readings An external digital sensor is also provided, with the digital output being communicated through a second opening within the enclosure A control member that receives, stores and processes the digital readings is positioned within the enclosure A communication module is included to transmit the digital readings to a remote computer The communication module allows for two way communication between the field instrument and remote computer The remote computer may be a server that allows for access by many users The communication module also allows for locally accessing the digital readings via a serial port to a local terminal

Dual mode USB and PCI express device

Abstract: A flash memory device for connecting to an ExpressCard™ host includes at least one flash memory module, an ExpressCard™ connector for connecting to the ExpressCard™ host, a first serial interface coupled to the ExpressCard™ connector, and a controller coupled to the first serial interface and the at least one flash memory module.

Method and system for providing a virtual universal serial port interface and a virtual storage interface

Abstract: A virtual universal serial port interface (“USI”) and a virtual storage device interface (“VSI”) interfacing with a host system and a remote console over a network link is provided. The USI includes a control register that receives control information from a processor and a legacy control register; and a status register that receives information from a legacy control register and based on that information, the processor formats information stored in a buffer destined for transmission over a serial port. The VSI includes, a first register that receives control information from a third register that stores control information sent by a processor used to update a fourth register that notifies the host system.

Multi-channel synchronization for programmable logic device serial interface

Abstract: A serial interface for a programmable logic device substantially eliminates skew across multiple channels both in the receiver and in the transmitter. Even when the channels are independent (e.g., are in different quads), skew is substantially eliminated by monitoring to determine when all channels have reached their active states (i.e., in the case of receiver channels when all channels have achieved byte alignment and have received an alignment character, and in the case of transmitter channels when all transmit PLLs have locked), and only then allowing data to flow between the serial and parallel domains.

Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers

Abstract: A serial port controller in an embedded disk drive controller is provided. The serial port controller includes a state machine that can access protocol information regarding plural devices operationally coupled to the serial port controller; a first register that can hold address information of the plural devices; and logic for enabling the plural devices for either a write or read request. The serial port controller also includes a second register for holding write data information for the plural devices; and a third register for holding read data information for the plural devices. The serial port controller reads programmed information regarding the plural device upon a client request; transmits the address of a device with whom communication is requested by the client; and transmits data to the plural devices, if the request by the client is to write data or collects data for a read request.

Communicating to system management in a data processing system

Abstract: A data processing system in which standard communication resource facilities are used to enable direct communication to a system management facility In one implementation, the management adapter shares a communication resource, such as a serial port, with the host system An arrangement of multiplexers is capable of connecting the local system to the shared resource, the management adapter to the shared resource, or the host system to directly to the management adapter The host system includes a device driver for the shared resource The shared resource device driver is leveraged to communicate to the management adapter using a standardized serial protocol (in the case of a shared serial port) when the multiplexers connect the system to the management adapter

Multi-channel programmable gain amplifier controlled with a serial interface

Abstract: A programmable gain amplifier (PGA) controlled through a serial communications interface are fabricated on an integrated circuit (IC). A multiplexer (MUX) may also be included on the IC. The serial communications interface controls the gain of the PGA, MUX channel selection, and other functions of the PGA. Status of the PGA may also be obtained through the serial communications interface. By using a serial communications interface, the pin count of the PGA IC package may be kept to a minimum.

GPS time synchronization in school-network cosmic ray detectors

Abstract: The QuarkNet DAQ card for school-network cosmic ray detectors provides a low-cost alternative to using standard particle and nuclear physics fast pulse electronics modules. The board, which can be produced at a cost of less than $500.00 (USD), produces trigger time and pulse edge time data for 2- to 4-fold coincidence levels via a universal RS232 serial port interface, usable with any PC. Individual detector stations, each consisting of four scintillation counter modules, front-end electronics, and a GPS receiver, produce a stream of data in form of ASCII text strings in identifiable set of formats for different functions. The card includes a low-cost GPS receiver module, which permits time-stamping event triggers to about 50 nanosecond accuracy in UTC between widely separated sites. The technique used for obtaining precise GPS time employs the 1PPS signal, which is not normally available to users of the commercial GPS module. We had the stock model slightly custom-modified to access this signal. The method for deriving time values was adapted from methods developed for the K2K long-baseline neutrino experiment. Performance of the low-cost GPS module used is compared to that of a more expensive unit with known quality.

Systems and methods for automatic assignment of identification codes to devices

Abstract: A system and method for automatically and uniquely assigning identification codes to a plurality of slave processors. A master processor having communication port is linked to a first slave processor, which, itself, has first and second communication ports. The first communication port is used in support of the aforementioned link to the computer. A second slave processor, also having first and second serial ports, is linked by its first communication port to the second communication port of the first slave processor. The slave processors are programmed to read designated pins on their first communication ports. The read values determine the identification code of each processor. Thereafter, each slave processor outputs to its second port a value one greater than the value read from its first port. Therefore, each slave processor assigns itself a particular identification code and directs the next slave processor to assign itself an identification code one greater.

Virtual keyboard and robot control system by brain electric signal

Abstract: Structure of the system is composed of purpose made hardware platform and control program. The hardware platform consists of PC, controller of brain-computer interface, robot and peripheral electrical appliances. Serial port of computer is connected to the controller of brain-computer interface. Brain electric signal through CPU and computer program controls virtual keyboard and robot. Advantages are: stable hardware, high recognition rate of software, realizing function of virtual keyboard to output English and Chinese. The invention is suitable to handicapped by using brain electric signal to make robot serve people.

Multi-energy power assembly semi-matter simulation testing system

Abstract: A semi-actual simulating test system for multi-energy power assemblage of car is a closed-loop one, and is composed of a desktop PC, 8-channel A/D acquisition card, a 8-channel D/A converter card, 32-channel I/O card, the digital signal generator connected to high-speed serial port's USB converter, and software developing platform Matlab/simulink to replace the dynamic calculation model of car assemblage.

Techniques for automatic eye-degradation testing of a high-speed serial receiver

Abstract: Embodiments of the invention relate to techniques for automatic degradation testing of a high-speed serial receiver. A transmitter manipulator couples to a transmitter of a serial interface circuit. The transmitter is coupled to the receiver of the serial interface circuit. The transmitter manipulator includes a storage to store one of current compensation values or impedance compensation values and sequencing logic to dynamically sequence the one of the current compensation values or impedance compensation values to the transmitter. The transmitter responsive to the dynamically sequenced one of the current or impedance compensation values generates a degraded test pattern signal to transmit to the receiver in order to test the receiver.

Software compatible parallel interface with bidirectional handshaking for serial peripherals

Abstract: High-speed reliable parallel data transmission between a computer and a parallel peripheral is provided by a peripheral controller by way of a virtual parallel UART (VPU). The VPU provides a novel parallel interface for higher speed parallel interface operation. The VPU is included in the peripheral controller along with a conventional RS-232 UART. The peripheral-side interface of the peripheral controller provides full bidirectional handshaking with the parallel peripheral. The host-side interface of the peripheral controller provides a legacy serial port compatible interface. Mode information selectively configures operation in either a VPU (parallel) or a UART (serial) mode. Both modes appear identical to software executing on the computer, enabling the use of standard serial I/O drivers without modification, and providing transparent legacy mode compatibility even when the hardware is configured for VPU mode.

Power amplifier with digital power control and associated methods

Abstract: In a power amplifier, a serial bus interface is provided for sending and receiving information to other devices, such as a baseband controller. The power amplifier includes several control pins that can be used as a serial interface, or alternately, with a direct pin control interface. The serial bus interface can be used with digital power control techniques that provide various advantages over conventional power amplifiers.

Series interface bus communications controller

Abstract: A bus communication controller of serial interface includes interface part consisting of serial asynchronous receiving-transmitting unit at the interface end and data buffering process unit 1, bus part consisting of serial asynchronous receiving-transmitting unit at the bus end and data buffering process unit 2 and communication control part consisting of communication control unit, circuit of error counting and error processing as well as detecting circuit of multiple address access collision to be monitored by carrier frequency.

Controller area network (CAN) controller module, for motor vehicle, has serial interface for connection to external computer unit, via which it can be freely programmed, and connected to CAN analysis and simulation module

Abstract: Controller area network (CAN) module comprises a microprocessor, CAN controller and a CAN transceiver together with a serial interface over which it can be connected to an external computer unit. The microprocessor is loaded with an operating system that can be configured via an external computer and the serial interface. The invention also relates to a corresponding device for configuring a CAN controller module that additionally has a CAN analysis and simulation module.

PLD debugging hub

Abstract: User logic within a PLD is debugged by way of the hub. The PLD includes a serial interface (such as a JTAG port) that communicates with a host computer. Any number of client modules are within the PLD and provide instrumentation for the PLD. A module is a logic analyzer, fault injector, system debugger, etc. Each client module has connections with the user logic that allows the instrumentation to work with the user logic. The hub communicates with each client module over a hub/node signal interface and communicates with the serial interface over a user signal interface. The hub routes instructions and data from the host computer to a client module (and vice-versa) via the serial interface and uses a selection identifier to uniquely identify a module. The hub functions as a multiplexor, allowing any number of client modules to communicate externally though the serial interface as if each node were the only node interacting with user logic.

Single line serial interface protocol

Abstract: The invention relates to a dot-to-dot serial terminal agreement of a single line. It includes, defining a time threshold value (TH); defining two opposite bit data when the low voltage time of signallines is smaller than TH or not smaller than TH; defining the indication of bit data input operation when the signal line is rising; defining a finishing operation of data frame when the low voltage is changing to a high voltage and the time period is not smaller than TH. The advantage is simple agreement, cheap hardware, and low expense on software. The serial communication is accomplished with only a single signal line, so the invention is adapted for the communication between SCM and peripheral equipment.

Serial peripheral interface and related methods

Abstract: A serial interface for communicating with peripherals may include a circuit for generating pointers to addresses in sections of a memory, and a circuit for serially transferring data from or to at least one peripheral connected to the interface that is coupled to the memory based upon requisite configuration commands. The interface may further include a control register coupled to the memory and to the serial transfer circuit for controlling data to be transmitted or received. The interface does not require that an external controller provide configuration commands each time data is transmitted or received because the memory sections for storing data may be divided in distinct memory spaces. That is, each memory space may store data for a respective peripheral connected to the interface. Moreover, another memory section may be used to store all of the configuration commands of the interface required for communicating with the peripherals.

Testing method and device for non-volatile memories having a LPC (low pin count) communication serial interface

Abstract: An electronic memory device monolithically integrated in semiconductor has a low pin count (LPC) serial interface. The memory device includes a memory cell array and associated row and column decode circuits. The memory device also includes a bank of T-latch registers to be addressed and accessed in a test mode for serially loading specific test data therein. The serially loading includes activating a test mode of operation by an address storage block for generating a corresponding signal, enabling the bank of T-latch registers in the device to serially receive a predetermined data set, and loading test data into the T-latch registers by using a LPC serial communication protocol.