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Showing papers on "Silicon on insulator published in 1968"


Patent
Else Kooi1
19 Nov 1968
TL;DR: In this paper, the authors describe a semiconductor device having an insulating layer having a first portion of silicon oxide without silicon nitride and a second portion of polysilicon oxide covered with silicon oxide, and these layers are provided so as to establish at the semiconductor surface certain desired concentrations or densities of semiconductive surface states and surface or oxide charges.
Abstract: Semiconductor devices are described having on a semiconductor surface an insulating layer having a first portion of silicon oxide without silicon nitride and a second portion of silicon oxide covered with silicon nitride. These layers are provided so as to establish at the semiconductor surface certain desired concentrations or densities of semiconductive surface states and surface or oxide charges in order to control the performance of the device.

22 citations


Journal ArticleDOI
TL;DR: In this article, a junction seal consisting of a metal-insulator-silicon (MIS) system of materials has been developed to replace the vacuum-tight encapsulation.
Abstract: Most semiconductor devices today have a costly vacuum-tight encapsulation that provides a microenvironment for high reliability and electrical connections to the circuit in which it is used. A junction seal consisting of a metal-insulator-silicon (MIS) system of materials has been developed to replace the vacuum-tight encapsulation. The MIS junction seal, consisting of platinum silicide-titanium-platinum-gold contacts and a Silicon nitride overcoat, provides the necessary encapsulation for high reliability. Electrical and mechanical connections are provided by gold beam-deads. During fabrication, the contact windows are opened in the deposited silicon nitride layer either by etching with boiling phosphoric acid using SiO 2 as a mask or by anodically converting the silicon nitride in the windows to a soluble oxide. The multilayer contact is then applied to complete the junction seal. The initial characteristics of sealed-junction transistors fabricated by the above methods were similar to those of the unsealed transistors. The reliability of the sealed-junction transistors determined by accelerated aging after an intentional sodium contaminafion of 1017atoms/cm2surpassed that of the standard silicon planar transistors sealed in a vacuum-tight enclosure.

18 citations


Proceedings ArticleDOI
01 Jan 1968
TL;DR: In this paper, the gate insulator consists of a double layer of silicon dioxide and silicon nitride, and at an energy level inside the silicon forbidden band, are traps with a density as high as 2×1014cm-2in the form of disorder states.
Abstract: Transistors with memory hawe been constructed in the form of MIS field-effect transistors in which the gate insulator consists of a double layer. Closest to the silicon is a silicon dioxide layer, no more than 15A thick. The importance of this layer will be discussed. It is covered by another layer, which may be silicon nitride, 200-800A thick. Aluminum oxide and silicon dioxide have also been tried as the second layer. At the interface between these two insulator layers, and at an energy level inside the silicon forbidden band, are traps with a density as high as 2×1014cm-2in the form of disorder states. These traps are donor type and may each give off an electron when the silicon is biased positively for a short time with respect to the insulator, turning the transistor ON. When the polarity is reversed the electrons are recaptured by the traps, neutralizing them and turning the transistor OFF. The charge transport is by tunneling.

3 citations



Proceedings ArticleDOI
Gordon E. Moore1
01 Jan 1968
TL;DR: In this paper, the present status of silicon device technology is reviewed in order to point out its limitations, and the limitations of most concern in these areas of wafer fabrication technology are those associated with improving process control and minimizing defects.
Abstract: The present status of silicon device technology is reviewed in order to point out its limitations. The combination of melt-doping, epitaxial growth, and oxide-masked diffusion allows, at least in principle, the construction of about any desired impurity configuration within the silicon crystal. Our present understanding of the silicon-silicon oxide surface allows the design and control of the important surface properties and makes available such important devices as MOS transistors. The limitations of most concern in these areas of wafer fabrication technology are those associated with improving process control and minimizing defects. Effort in this area takes the form of relating cause to effect followed by appropriate detailed process changes. It represents a direction of extreme importance in maximizing the impact of silicon devices through greatly reduced cost.

2 citations


Journal ArticleDOI
TL;DR: In this article, it was shown that the higher dielectric constant and passivating qualities of the nitride are of value, and the electrical properties of the silicon/silicon dioxide interface can be controlled by existing technology.
Abstract: Results are presented which show that silicon nitride deposited directly onto silicon is of limited value for use in MIS devices, mid that most of these limitations can be removed by using the nitride in sandwich structures with thermally grown oxides. Tn such structures the higher dielectric constant and passivating qualities of the nitride are of value, and the electrical properties of the silicon/silicon dioxide interface can be controlled by existing technology. Associated Semiconductor Manufacturers Limited is a joint Mullard/G.E.C. company responsible for the development and manufacture of Mullard semiconductor devices.

2 citations