Showing papers on "State (computer science) published in 1976"

Programmable controller using microprocessor

Abstract: There is provided a programmable controller comprising a standard microprocessor having output address terminals and input/output bi-directional data terminals and means for providing a binary code on the data terminals indicative of the status of the machine cycle to be processed by the microprocessor This programmable controller includes a logic decoder means for producing a selected signal in response to logic signals on selected address terminals and in the status binary code of the data terminals In addition, the programmable controller includes means for programming the HOLD state for the microprocessor There is also provided an arrangement for expanding the number of interrupt conditions which can affect the INTERRUPT state of the microprocessor in the programmable controller

Programmable tester method and apparatus

Abstract: A method and apparatus for automatic, programmed, in-circuit testing of individual logic elements. A plurality of program-operated device connection switches are provided for making connections to the circuit under test. A plurality of program-operated drive circuits are provided for driving nodes of the logic element under test with controlled current, voltage and power to logical 1, logical 0, or a high impedence state. A measurement unit measures an output from the logic element under test. Testing programs are run in a program-controlled processor. The programs have subroutines which correlate with individual types of logic elements. Each logic element is examined, in circuit, independently of neighboring logic elements. A translation memory stores data for translating node addresses to facilitate topology independent subroutine processing of identical elements.

Digital load control circuit and method for power monitoring and limiting system

Abstract: To maintain power consumption within predetermined limits, the ON/OFF states of a plurality of electrical loads are controlled by a digital load control circuit that forms part of a closed-loop control system. The power consumed by the ON loads is monitored and compared with a reference and in response to such comparison command signals are produced that instruct the digital circuit to add or shed loads as required, to increase or decrease, respectively, the power consumption. Inputs to the load-control circuit are in the form of one or more add or shed command pulses wherein the former instructs the circuit to add a load, and the latter instructs the circuit to shed a load. To execute these commands, the load-control circuit includes a reversible, recycling address generator that successively addresses a bank of addressable latches, one for controlling the ON/OFF state of each load. As the latches are successively addressed, logic circuitry operates to detect a concurrence of an add command and an OFF load state at the addressed latch, or a concurrence of a shed command and an ON load state at the addressed latch. Detection of the former set of conditions causes the then addressed latch to be switched from its load OFF state to its ON state and detection of the latter set of conditions causes the then addressed latch to be switched from its load ON state to its OFF state. Various embodiments of the foregoing are disclosed including circuitry for selectively dividing the plurality of loads into two different groups, one of which is a fixed priority group wherein the loads thereof are added and shed in a fixed order, and the other of which is a rotate group wherein the order that the loads are added and shed is rotated so that all of the loads of such group equally share the available ON time; and circuitry for selecting a limit to the total number of rotate loads that can be ON at any given time and a limit to the number of such loads that can be OFF at any given time.

Method of propagation delay testing a level sensitive array logic system

Abstract: Propagation delay testing is performed on a generalized and modular logic system that contains embedded arrays and can be used as arithmetic/logical/control unit in a digital computer or data processing system. Each such unit can be composed of combinatorial logic and storage circuitry. The storage circuitry may be of two types, randomly arranged latches, or arrays of storage cells. In the organization presented here the latches are arranged such that they have the capability of performing scan-in/scan-out operations independently of system control. Using this scan capability, the method of the invention provides for the state of the storage latches to be preconditioned and independent of prior circuit history. Selected propagation paths are sensitized by patterns from an automated test generator or designer supplied patterns. By alternating selected inputs and by applying proper timing control, propagation delay indications through the selected paths are obtained to determine delay behavior of the logic system.

Asynchronously operating signal diagnostic system for a programmable machine function controller

Abstract: A diagnostic apparatus for use with a programmable machine function controller having a memory for storing a machine control program wherein the controller continuously scans the memory and generates output signals in response to input signals having signal states corresponding to the desired states as defined by the machine control program. The diagnostic apparatus includes a second program for testing the input signals as they are required by the machine control program to execute cycle steps and cycles of operation relative to the machine. The diagnostic apparatus operates asynchronously with the machine function controller to sequentially check the cycles of operation, many of which may be occurring simultaneously. In checking each cycle of operation, the diagnostic apparatus checks each cycle step and further checks the state of each input signal associated with each cycle step. The diagnostic apparatus is operative to continuously display a representation of the failure conditions detected. Finally, the apparatus detects and displays a representation of input signal failures which are independent of any of the cycles of operation associated with the machine.

De-glitchable non-metastable flip-flop circuit

Abstract: Title of the Invention DE-GLITCHABLE NON-METASTABLE FLIP-FLOP CIRCUIT Abstract of the Disclosure The flip-flop circuit of the present invention is one that cannot glitch or enter a metastable hang-up state and has a probability of one of being completely settled at some given finite time following clocking. The flip-flop circuit is com-prised of an input logic gate, an integrator and a logic latch circuit. In operation, the input logic gate changes state upon the coincidence of input signals,which change in state causes the integrator to change output level at a controlled rate. The latch circuit is sensitive to the output level of the integrator and changes state only when the integrator's output level reaches or exceeds preselected thresholds.

Address buffer circuit for high speed semiconductor memory

Abstract: A high speed address buffer circuit for use in MOS/LSI semiconductor memories or the like. An unbalanced, dynamic cross-coupled pair of MOS driver transistors is used to sense an address input during a short time window, and internal address signals are generated from the state of the sense circuit. Sensing nodes are precharged and equalized prior to the time window, and the node which is to stay at the logic "1" level is held at a high level by boosting capacitors to which a delayed clock signal is applied. The state of the sense circuit is sampled at a time after the delayed clock and high level addresses are generated.

Input-output control circuit for FIFO memory

Abstract: In transmitting data between a plurality of sequentially connected FIFO type memory elements by controlling a binary coded signal a circuit element is provided in a manner to correspond to each memory element, so as to indicate a data storage state. A circuit element comprises flip-flop constructed of two NOR circuits, the input of each NOR circuit being connected to an input control line or an output control line, and inverters each of which is connected to the output of the NOR circuit. The provision of such circuit element permits an automatic data transmission control according to a data storage state in a specified memory element and a data storage state in the next stage memory element.

A Study of Practices of Elementary School Supervisors (K-8) in the State of Louisiana as Perceived by Supervisors of Instruction, Principals, and Teachers.

Abstract: The primary purpose of this thesis was to study practices of elementary supervisors of instruction (K-8) in the state of Louisiana as perceived by supervisors of instruction, principals, and teachers during the 1974-75 school year. From supervisor of instruction practices found in current literature, comprehensive check lists of tasks of supervisors of instruction were devised for elementary supervisors of instruction, principals, and teachers. Tasks were categorized as directly, possibly, or indirectly related to the improvement of instruction, and those having little or no relation. Items in each of the three check lists were matched for comparative purposes. Of 66 parish and city public school systems, 59 participated in the study. The total sampling consisted of 585 possible respondents employed during the school year (231 supervisors of instruction, 118 principals, and 236 elemen­ tary teachers). Net returns were; 137 supervisors of instruction, 59.3 percent; 79 principals, 66.9 percent; and 144 teachers, 61.0 percent. Total net returns were 360 check lists, 61.5 percent. The findings were:

Threshold integrated injection logic

Abstract: Integrated injection logic circuits and semiconductor devices employing threshold functions. Multiple-collector input transistors have their collectors connected to the bases of one or more output transistors. The output transistors have different injection current levels. The switch-ing states of the output transistors are functions of the number of and conduction state of input transistors to which the output transistors are connected and to the weight of the injection current associated with the output transistor.

The Impact of Speech Training on Oral Communication Performance in Industry as Perceived by Louisiana State University Graduates, 1950-1967.

Abstract: Since businessmen testified in trade journals that oral communi­ cation played a major role in the industrial setting, a methodology was devised to compare speech preparation with perception of on-the-job oral communication performance of 176 Louisiana State University gradu­ ates employed in industry in the Baton Rouge area. Research was de­ signed to gain insight into the effectiveness of speech preparation from the viewpoint of the graduate in industry. The 250 graduates studied received a B.A. or B.S. degree from Louisiana State University during the period 1950-1967, and comprised three groups divided on the basis of advanced, basic, or no speech training. Responses from 70.4% of the sample provided the necessary data through a combination of interviewing and a detailed questionnaire. The researcher compared the perceptions of the three speech train­ ing groups, management level, level of speech training, age, and company size. A second design compared the data obtained by the questionnaire on speaking performance to the level of speech training. The third and final design compared speech course grades and number of courses coml pleted to speaking performance. Using the Statistical Analysis System, a computer synthesized, correlated, and placed variables in the necessary arrays. Most of the university graduates were 30-49 years of age and com­ pleted college courses in speech. They represented all management levels and over 45% worked in companies with 500 or more employees. The data elicited from them indicated that speech training did affect the Louisiana State University graduate’s perception of his speaking ability on-the-job. The null hypothesis, that there is no relationship between speech training and the Louisiana State University graduate’s perception of his oral communication performance in industry,has to be rejected and the following conclusions deduced: 1. Both speech training groups perceived themselves as better communicators than the graduates without speech training in 96% of the responses. 2. Perception of speaking performance improved with advanced speech training. 3. All three speech training groups ranked their perception of the order of occurrence of the five speech activities as (1) meetings, (2) conversation, (3) listening, (4) and (5) group discussion and conferences, and (6) formal talks. 4. As speech training increased, the number of respondents listing formal talks as one of the three most frequently experienced activities also increased. 5. The chances of being in the upper management levels increased markedly for graduates with advanced speech training. 6. A marked increase in grade average occurred for graduates with advanced speech training in top management positions. 7. A positive correlation existed between perception of speaking performance and instructor grade evaluation. 8. Finally, the graduate that had a better perception of his speaking performance also assigned more value to his speech training.

Multi-bootstrap driver circuit

Abstract: Plural bootstrap capacitors are coupled to an output stage of a MOSFET driver. A conventional bootstrap driver is preceded by one or more additional bootstrap stages. Each one includes a capacitor, a tri state inverter and a delay section. When the output stage is off all capacitors are discharged. To turn the output stage on, all capacitors, including the output gate capacitance, are charged in parallel. Then each capacitor in turn is caused to pump its charge into the gate of the output stage, with the last capacitor pumping the output stage gate voltage to a level well in excess of the applied power supply voltage.

The state of the Art of Computer Programming

Abstract: This report lists all corrections and changes to volumes 1 and 3 of "The Art of Computer Programming," as of May 14, 1976. The changes apply to the most recent printings of both volumes (February and March, 1975); if you have an earlier printing there have been many other changes not indicated here.

Job Satisfaction Among Faculty Women in Higher Education in the State Universities of Louisiana.

Abstract: The major purpose of this study was to analyze and to quantify environmental work elements which affect job satis­ faction of faculty women in state universities of Louisiana. Additional purposes were to determine degree of job satisfac­ tion among faculty women in higher education, to learn whether job satisfaction of these women was affected by independent variables, to profile respondents and to investigate their career patterns. A stratified random sample of three hundred was se­ lected from the total population of the 1975-76 faculty women employed in the state universities„ Two hundred and twenty of the three hundred questionnaires mailed were returned. The Minnesota Satisfaction Questionnaire (MSQ) and The Se­ lected Life History Items of Women in Higher Education (selfdesigned) were used to collect data. The twenty sub-scales of the MSQ were analyzed by mean and standard deviation to determine what aspects of their jobs gave faculty women most satisfaction. Factors contributing most to feelings of satisfaction were moral values, social service and activity. Aspects supplying least job satisfaction were university policies and practices, ad­ vancement and compensation. The mean of the respondents' scores on the general satisfaction portion of the MSQ was examined to determine

Central processing apparatus for generating and receiving time division multiplex signals

Abstract: A central processing apparatus for use in a system which includes a plurality of remote electrical devices and a multiplex signal transmission line coupled to each of the plurality of devices. The central processing apparatus comprises an input unit coupled to the multiplex signal transmission line for receiving state signals from the plurality of devices in a time division multiplex format representing the states of the plurality of devices; an output unit coupled to the multiplex signal transmission line for transmitting logically processed signals to the plurality of devices in a time division multiplex format to control the plurality of devices; a logic processor responsive to the receiving of the state signals to generate the logically processed signals; a memory coupled to the logic processor, the input unit, and the output unit, for storing the state signals received from the plurality of devices and the logically processed signals generated by the logic processor; and a stored program control section coupled to the memory, the logic processor, the input unit, and the output unit for controlling the operation thereof.

Automotive vehicle speed control system

Abstract: To provide for digital storage of a command signal commanding a predetermined speed of the speed control system, a digital counter is provided forming a memory, connected to an analog-digital converter to generate a derived command signal in dependence on the counted state of the counter. Stray signals which may affect the count state of the counter thus can only change the time at which the counter reaches its predetermined count state, and not the count output thereof, whereas such stray pulses might otherwise affect the command signal. The counter holds the commanded speed as a count number.

Error display system

Abstract: PURPOSE: To show accurately the occurrence area and the state of an error by securing a display for the error symbol and the contents of the error, and thus to simplify the check operation. COPYRIGHT: (C)1978,JPO&Japio

Automatic rhythm performing apparatus

Abstract: A control circuit for controlling an automatic rhythm generating circuit of an automatic rhythm performance apparatus comprises a memory for controlling the rhythm start or stop operation of the automatic rhythm generating circuit by an output state, a rhythm performance control signal supply circuit including a plurality of rhythm performance control switches, and a logic circuit having inputs coupled to the outputs of the rhythm performance control signal supply circuit and to the outputs of the memory and having outputs coupled to the inputs of the memory. The state of signals at the outputs of the rhythm performance control signal supply circuit is variable by the operation of the control switches. The logic circuit causes the memory to be set from one output state to another state in response to a variation in the state of signals at the outputs of the rhythm performance control signal supply circuit.

Counting circuit system for time-to-digital converter

Abstract: In an analog to digital converting circuit used in a pulse height analyzer or in a time to digital converting circuit used in a time analyzer, the first binary in a scaler for counting clock pulses is switched over to use the true state and the complementary state each of the reset circuit and the output circuit, alternately. By switching over the reset circuit and the output circuit, no substantial variation in counting the scaler is induced and any odd-even unbalance phenomena due to the binary constitution of the scaler is statistically equilibrated.

The Viability of Multimicroprocessor Systems

Abstract: The advances made in integrated circuit technology to date have been dramatically greater than the uses which have been made of this technology. Initially, the only use of LSI was for the construction of various types of memories. This is an obvious first choice since memories offer both an orderly repetitive pattern, making implementation easy, and a high gate-to-pin ratio, making very large numbers of gates possible on a single chip. The success achieved with memories has caused the processor part of a computer's hardware cost to become increasingly more expensive relative to the memory. As long as the processors are constructed from SSI/MSI units, they will continue to become relatively more expensive as the state of the integrated circuit technology continues to advance. So, a major challenge facing computer designers is to create techniques for utilizing the considerable capability available in LSI technology in the construction of the processing portion of computing systems.

Highway investment analysis package

Abstract: The highway investment analysis package (HIAP), a computerized evaluation and investment programming model, has been developed for the Federal Highway Administration to aid state, regional, and local organizations in making the best use of limited highway funds. HIAP uses microeconomic theory to analyze individual roadway sections and limited networks of sections specified by their physical, traffic, and operational characteristics. Estimates of both highway user (i.e., vehicle operating costs, travel times, and accidents) and nonuser(i.e., noise levels and air pollutant emissions) impacts are produced. HIAP develops multiperiod investment programs by selecting those improvements that maximize either user benefits or one of several accident reduction measures. The selection process permits consideration of a broad range of funding constraints, which may be tailored to the specific needs of individual organizations. Based on marginal analysis, the process allows consideration of multiple alternatives and staged improvements at each analysis site. Great flexibility in the contant and format of input data is afforded the analyst. Furthermore, HIAP includes a transformation program that allows the analysis of data already available in the format used for the 1970 to 1990 highway needs study.

A unique graduate program in computer science at Jackson State University

Abstract: The two key elements of decision-making in today's environment are (i)efficient information processing and management and (ii) a degree of maturity in effective use of a broad range of analytical tools and techniques which pass under the general label of Mathematical Sciences.The Department of Computer Science at Jackson State University started a Graduate Program during the 1974 academic year which offers a unique interdisciplinary program leading to a Master's Degree in Computer Science. This program emphasizes in programming languages, systems programming, operating systems, information systems analysis and design, the role of the computer as an integral part of the decision-making process, and the computer applications in the areas of statistics and management science. Advanced placement may be given via examination or acceptable certificate presentation from traditional or non-traditional institutions such as IBM Corporation. The students are presently using both the interactive and the batch capability of our IBM 360/40 for their course and project works. The university is upgrading to an IBM 370/145 during the spring semester (1976).

Line communications system for stations in tandem - has identical modules with logic decision circuits connected with intermediate registers

Abstract: The communications system for stations connected in tandem consists of a number of identical communications modules, each being connected by line and fitted with monitor circuits for the detection of line or station faults. The lines (31, 38) are connected to address identification circuits (25) and registers. The gate operates to re-route the information if it is not intended for that particular station. A decision circuit (21) decides whether data is stored in an intermediate register when the station itself is transmitting. A gate (23) controls the flow of data between the operating unit (11) and the store (22). The monitor unit (27) uses a time code to monitor the state of the line and to detect errors. It operates in conjunction with the decision circuit and initiates data shuttling when it is at the start of a transmission leg within a system section.

Computer-controlled display demonstrations of dynamic concepts in computer science

Abstract: Computer Science contains a large number of new concepts well outside most students' prior experience. An important characteristic of many of these concepts is their dynamic nature: the execution of a program, assignment of a value to a variable, change of machine state following an interrupt, convergence on a root. By using the computer itself as my demonstration apparatus, I propose to give the students personal exposure to the concepts in action. With a low-cost interactive CRT terminal and video projector, I can show various aspects of a program executing, for instance, at comparatively low investment in machine and people time.

File Input/Output Control Logic

Abstract: This paper focuses on a key issue in operating system design that has hitherto received no explicit attention in the literature–file input/output control logic. Particular attention is concentrated on two well-known systems: the IBM System/360 under OS, and the Burroughs 1700 under the Master Control Program.

A state of the art survey on linear phase digital filter design

Abstract: Following a brief review of digital filters and associated terminology, the problem of linear phase design is stated in precise form. The relative difficulty of IIR design as compared to FIR design is discussed and a state of the art survey is presented for both cases.

Subscriber monitoring unit for electronic telephone exchanges

Abstract: The monitoring peripheral equipment is intended to inform the exchange's central unit about the state and nature of the subscriber's receiver and it comprises: a circuit sensing the positions of the relays of the line equipment, a memory unit, an internal logic with a scanner thereof, a liaison circuit logic and a line equipment monitoring device, whereby the lifting of a subscriber's receiver is detected, the information is sent to the internal logic as regards the location, state and processing to be performed, said central unit calls back said liaison circuit logic and the internal logic sets the subscriber's telephone in the connected position.