Showing papers on "State (computer science) published in 1982"

Logic for improving integrity checking in relational data bases

Abstract: When an "updating" operation occurs on the current state of a data base, one has to ensure the new state obeys the integrity constraints. So, some of them have to be evaluated on this new state. The evaluation of an integrity constraint can be time consuming, but one can improve such an evaluation by taking advantage from the fact that the integrity constraint is satisfied in the current state. Indeed, it is then possible to derive a simplified form of this integrity constraint which is sufficient to evaluate in the new state in order to determine whether the initial constraint is still satisfied in this new state. The purpose of this paper is to present a simplification method yielding such simplified forms for integrity constraints. These simplified forms depend on the nature of the updating operation which is the cause of the state change. The operations of inserting, deleting, updating a tuple in a relation as well as transactions of such operations are considered. The proposed method is based on syntactical criteria and is validated through first order logic. Examples are treated and some aspects of the method application are discussed.

Direct Implementation of Asynchronous Control Units

Abstract: The "one-hot" row assignment for asynchronous circuits, in which every row in a flow table has exactly one of the feedback variables that equals the value 1, provides a straightforward method for circuit synthesis. Once a flow table has been constructed, the state equations can be directly written, without requiring any procedure to ensure a race-free assignment. Furthermore, it can implement any arbitrary fundamental mode asynchronous circuit, not depending on a specific signaling protocol for its correct operation. An alternate view of one-hot asynchronous circuits is given, with a simple set-reset flip-flop for each state. Although this may seem excessive compared to implementations with encoded state variables, for many circuits their one-hot implementation is comparable in cost to other asynchronous implementations.

From State Machines to Temporal Logic: Specification Methods for Protocol Standards

Abstract: This paper attempts to lend perspective to several different methods that have been employed for specifying computer communication protocols by comparing a spectrum of specification techniques. The paper characterizes specification languages such as state transition diagrams, variants of temporal logic approaches, and sequence expressions by the extent to Which information is encoded as properties of a single state versus properties of a history of the entire computation state sequence. Taking the prototypical alternating bit protocol as an example, each method is used to specify the requirements for the send process of the distributed system.

Multiprocessor interface device

Abstract: A single chip multiprocessor interface device for interfacing between two processors by connection to their bus systems, the device having a random access memory selectively accessible by the processors under the control of an arbitration latch. The arbitration latch has a bistable device the state of which determines which processor has access to the memory. The outputs of the bistable device have threshold devices which have threshold levels higher than the signal outputs of the bistable device when it is in a metastable state, so that there is no possibility that both processors could have access to the memory at the same time. Data and address registers for the two processors are selectively connectible to the random access memory through multiplexers controlled by the arbitration latch. Mode control inputs can set the device into a "stand alone" mode, a "master" mode and a "slave" mode; several devices can be used in parallel for bus systems more than one byte wide with one device the master and the others slaves. Control and status registers for each processor input enable the generation of interrupts when certain conditions are met.

Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof

Abstract: Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. A mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip. The application of this method requires partitioning that makes each identified high performance subset executable on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a technology in which it is economically feasible to have several copies of a complex data flow and control store mechanism.

Branch predicting computer

Abstract: 0 Disclosed is a digital computer which includes means for storing a plurality of instructions arranged as a program with conditional.branch instructions at respective locations in said program specifying conditions to be tested; an instruction prefetch means and an instruction execute means for respectively fetching and executing different instructions of said program at the same time in a pipelined fashion; said conditional branch instruction at each of said locations further having multiple encodings which predict the state of the condition to be tested; and a control means for detecting when said prefetch means has fetched one of said conditional branch instructions and for fetching the next instruction based on the predicted state of the condition to be tested and encoded in said fetched conditional branch instruction.

Partial traceback and dynamic programming

Abstract: Dynamic programming is used in speech recognition to search efficiently for word sequences whose templates best match acoustic data. The search is constrained by finite-state networks embodying grammatical rules. Typically, dynamic programming is implemented in two steps: the first calculates, for each state in a network and for each time, the best way of arriving at that state at that time; the second traces back from the final state at the final time to the initial state at the initial time to determine the best path through the network. This second step cannot be initiated before the determination (usually from the detection of silence) that the final state has been reached. Such a determination is difficult in the recognition of truly continuous speech; there are often no reliable anchor points. Further, it is often desirable to be able to recognize at least part of an utterance before a speaker has stopped talking. In this paper we introduce a technique for discovering the initial section of the optimal path through a network before the traversal of the network is complete. It can be used to report a system's interpretation of acoustic data from the not-too-distant past without relying on or making any decisions which may degrade recognition accuracy.

Multi-station token pass communication system and method

Abstract: A data communications system is disclosed which uses a passive communications medium such as coaxial cable for communication between multiple stations connected to the bus. A token concept is employed such that when the token is owned by a station, it allows that station to transmit high level messages over the bus and to command, if desired, other stations to transmit high level messages to it. The communications system is primarily masterless with each station capable of token ownership using the same set of rules to determine the circumstances when perceived events by the station cause that station to change state. Improvements are presented in the initialization of a token list, the addition of stations to an existing token list, duplicate station address protection through random numbers associated with each station, power down patch out of a station from the token list, the joining of two networks (two token lists), timer period randomization, and the use of redundant communication mediums.

Software protection method and apparatus

Abstract: In a microprocessor system, data stored in a protected memory (12) within the same housing as the microprocessor (10) are secured by enabling access to the contents of the memory in response to an instruction only if the instruction was previously fetched from the memory (12). Protection circuitry (14) comprises a decoder (22, 24) responsive to the output of a status register in the microprocessor to operate a status signal when the microprocessor is in an instruction fetch machine cycle. The status signal is stored (26) until the protected memory (12) is selected by the microprocessor (10). Access to data in the protected memory (12) is enabled only if the status signal is stored during memory select or the microprocessor is in an I/O machine cycle for communication with a peripheral. In addition, voltage controlled switches within the housing place the bus in a HALT state during memory select unless the microprocessor is in an I/O machine cycle. The protection circuitry (14) is disabled by a fuse (36) within the housing for memory content verification. Following verification, the fuse (36) is blown to secure the memory (12).

Electronic control system in a glassware forming machine

Abstract: The machine has a plurality of individual glassware forming sections each having a plurality of glassware forming mechanisms and means for distributing gobs of molten glass to each of the individual sections in an ordered sequence over one machine cycle consisting of a fixed number of clock pulses by cycling the forming mechanisms in a predetermined sequence of forming steps. Each individual section has an electronic control system responsive to each clock pulse for providing a load signal and forming signals to actuate the forming and a circuit for providing a gob load signal in response to a load signal from any one of the control systems and means responsive to the absence of a gob load signal for deflecting a gob from being distributed to an individual section. The machine has means for providing an operation pulse each time the control system provides forming signals to the forming mechanisms and means for providing a monitoring signal at a first binary state when a first one of the operation pulses is applied and changing to the second binary state if no operation pulse occurs within a stall-period of time after the first operation pulse. Each system also comprises means for enabling the load signal and the forming signals when at the first binary state and for inhibiting the load signal and the forming signals when at the second binary state so that the gobs of molten glass will not be distributed and the mechanisms will return to a safe condition.

From state machines to temporal logic - Specification methods for protocol standards

Abstract: This paper attempts to lend perspective to several different methods that have been employed for specifying computer communication protocols by comparing a spectrum of specification techniques. The paper characterizes specification languages such as state transition diagrams, variants of temporal logic approaches, and sequence expressions by the extent to Which information is encoded as properties of a single state versus properties of a history of the entire computation state sequence. Taking the prototypical alternating bit protocol as an example, each method is used to specify the requirements for the send process of the distributed system.

Polygraphic encryption-decryption system

Abstract: A system for encoding, or encrypting, digital data wherein an invertible matrix of binary bits provides the encrypting factor or key, this invertible matrix being loaded in a memory. Blocks or sets of binary bits of data, a string of serially appearing binary bits, to be encoded are sequentially loaded into discrete, ordered stages of an input shift register, and the state of each stage is coupled as an enabling signal to sets of gates which read out the binary states of rows of the matrix configured memory. Groups of outputs from gates, conforming to columns of the matrix memory, are fed to an exclusive OR gate for each group. Then, the outputs of the exclusively OR gates for several columns of the matrix are loaded into discrete stages of an output register. The combination of the states of the output register together provide a block or polygraphic encryption, or decryption, of the binary data supplied the input register. The states of the output register are then clocked out in serial form.

Fail-safe circuit for a microcomputer based system

Abstract: A fail-safe protection circuit for a data processor controlled system having a data bus for carrying data and comprising first logic for checking the operation of the data processor controlled system at periodic intervals not greater than T 1 and for producing a trigger pulse at each check if the data processor is operating properly, second logic for detecting the absence of trigger pulses for a time period T 2 to produce a control signal. Gating logic is responsive to the control signal to prevent the transmission of data through the data bus and a control circuit is also responsive to the control signal to reset the system to a predetermined operating state. The first logic responds to the resetting of the system to again produce the periodic trigger pulses if the system is operating properly.

Protection circuit for memory programming system

Abstract: A protection circuit inhibits the generation of a write-erase signal to an E2 PROM when the logic supply voltage falls below a predetermined threshold level. A differential-input amplifier compares the logic supply voltage with a fixed potential and when the logic voltage drops below the threshold, a transistor coupled to the write-erase signal generator switches to its conductive state inhibiting further occurrences of the signal.

System for simultaneously programming a number of EPROMs

Abstract: A method and system are used for simultaneously programming a group of erasable programmable read only memories (EPROMs) (11) originally set in the "all-ones" state, by routing (17-49) programmed bytes, bit by bit, to each memory site on each EPROM and blocking (48) or bypassing the programming steps where a programmed byte consists of all ones, thus saving the programming time that would be normally used to program "all-ones" sites Each programmed site and the sites set in the "all-ones" state are verified (52) prior to the routing of subsequent programmed bytes

Overcurrent display device

Abstract: An overcurrent display device is described which is suspended directly from a distribution cable for locating the spots of earthing, short-circuiting or other accidents in a distribution line system and is adapted to display the passage of the transient overcurrent due to such accidents through the cable for a predetermined time and to be restored to the original state before the display of the overcurrent condition. The device consists of an overcurrent sensing circuit, a drive unit including a drive element driven by the sensing circuit and a display unit actuated by the drive unit and adapted to achieve a display operation.

Method and network for improving transmission of data signals between integrated circuit chips

Abstract: A method and electronic network for limiting the electrical noise arising during transmission of digital data signals from a first integrated circuit having multiple output devices at which the data signals are formed to the input of a second integrated circuit. The method and network feature steps and means for sensing the conduction state of the first integrated circuit devices and for generating a control signal to invert the data signals before transmission when the number of output devices conducting is equal to or greater than a predetermined number. The method and network also feature steps and means for transmitting the data signals and control signal so that the data signals may be reconstituted to establish the data signals as they appear at the first integrated circuit output, before the data signals are presented to the second integrated circuit input.

Digital computer operation of a nuclear reactor

Abstract: A method is described for the safe operation of a complex system such as a nuclear reactor using a digital computer. The computer is supplied with a data base containing a list of the safe state of the reactor and a list of operating instructions for achieving a safe state when the actual state of the reactor does not correspond to a listed safe state, the computer selects operating instructions to return the reactor to a safe state.

Verification of communications protocols and abstract process models

Abstract: Communications protocols are crucial for the reliable exchange of information in distributed systems. In this dissertation, we consider the problem of formally specifying and verifying properties of protocol systems. Such systems are modeled by hierarchies of concurrent processes, where interprocess communication is achieved by message passing rather than through arbitrary shared variables. Based on this model, a methodology is developed for mechanically assisted protocol analysis. The Gypsy methodology for concurrent program verification is the point of departure for much of this work. Specialized methods applicable to protocols are derived from the Gypsy methods. Behavior of protocol modules is specified in a fairly abstract manner using a state transition paradigm, thus avoiding a highly procedural form of specification. Protocol services are specified by means of assertions over message histories. Proof techniques are introduced for verifying safety properties of the process models. In addition, a specification and assertion language is developed. This language emphasizes features and operations useful for expressing protocol oriented concepts and constructing proofs about them. An important aspect of this work is use of machine assisted analysis, most notably the use of mechanical theorem proving. A strategy for applying a particular automatic theorem prover, the Boyer-Moore prover, to protocol verification problems is put forth. A consequence of this strategy is the accumulation of a large body of proved lemmas, constituting a rudimentary deductive theory for protocols. With this theory, the methodology has successfully been applied to a pair of sample transport protocols. These include the Stenning protocol and an abstraction of the data transfer function of TCP.

Program validation: The state of the art

Abstract: Chad D. Ellett, PhD Director of Research and Evaluation Mathemagenic Activities Follow Through Program University of Georgia Athens, Georgia PROGRAM VALIDATION as a form of evaluation research provides information that is useful and relevant to school improvement efforts as well as information that can be used in the development and refinement, and adoption/adaptation and dissemination of educational innovations. Program validation is defined here as a form of decision-oriented research (as opposed to conclusion-oriented research, Tukey, 1960) that provides information about an educational intervention program that can be used to make decisions about its use at a particular time, for a particular purpose, and under particular conditions. Such an approach to program validation requires a data base on a program's implementation as well as its effectiveness. Innovative educational interventions that effectively improve student learning can have

Internal combustion engine having plural power sources

Abstract: PURPOSE:To stable a stable output in good timing and prevent delay of a response both at rapid acceleration and moderate acceleration, by changing the timing of starting the other power source in accordance with a state of acceleration. CONSTITUTION:The change of an acceleration state is converted into a change of electric potential by a slider 76 and input to a differentiation circuit 87, then a change of the signal is differentiated by this differentiation circuit 87 and input to a decision circuit 88. The decision circuit 88 varies the timing for starting a starter 85 in accordance with variation of the electric potential, to output a starting signal respectively at early timing in case of rapid acceleration while at delay timing in case of moderate acceleration. In this way, in case of rapid acceleration, the second engine 2 is previously started, when a throttle valve is fully opened, an electromagnetic powdery clutch 42 is directly connected for stable rotating motion of the second engine 2, while in case of moderate acceleration, the second engine 2 is started immediately before the throttle valve is fully opened.

The design of a multi-microprocessor based simulation computer - III

Abstract: This paper presents further results in development of a discrete event simulation computer based on a network of micro processors. The network is being designed by identifying simulation tasks which may be performed in parallel with other computation required by the simulation, and then assigning those subtasks to attached processing elements in the network. The tasks of priority queue processing and state accounting are considered in this paper. A three attached processor simulation computer has been designed, using two processors for the event set and the third for state statistics accumulation. In a simulation model of this system, a forty to fifty percent reduction in the execution of a benchmark simulation program is easily achieved. (The benchmark program itself uses an adaptive scheduling algorithm). Further observations and suggestions for future research are presented.

Program debugging device of computer

Abstract: PURPOSE:To increase the debugging efficiency, by displaying the state of execution of a program to be debugged in a 2-dimensional way and in correspondence to a plan of program. CONSTITUTION:The execution process of a program to be debugged at a computer process part 1 is rcorded sequentially to a recording part 6 through an interface 4 and a control part 5 and then displayed on a display part 10 based on the conditions given from an input/output part 11 and under the control of the part 5. The result of execution obtained at that moment is equal to the instruction code of machine word and the internal state such as the contents of a program counter, other register etc., and the program code is stored previously in a storage part 7. Thus the working state can be displayed after developing it into an easy-to-see form in contrast to the program code.

Active high before open three state integrated circuit output stage

Abstract: A three state inverter driver is operated so that its output goes to a logic one briefly just prior to going to its high impedance state when commanded by a disable pulse. This characteristic is useful where a plurality of drivers are employed to operate a DRAM element.

Optical multiple output display system, particularly for automotive dashboards

Abstract: To provide for optical indication of output values relating to the operating conditions, or other parameters for display on the dashboard of a display panel, for example on automotive vehicles, a display panel (10) has a plurality of indicating blocks (15a . . . 15k) distributed thereover. A logic circuit, for example provided by a micro-processor (12) supplies data over data busses (21, 41) to the respective indicating blocks, which can be connected in series (FIGS. 2, 4) or in parallel (FIGS. 5-7). The logic circuit is connected through suitable connecting lines (13) with sensor inputs, providing ambiant, or operation or operating data. The logic circuit, additionally, generates data of its own, for example time outputs. The indicating blocks each include a shift register (17, 18, 50) which is connected to a data line, the stages of the shift register being connected to respective indicating elements (16, 53) which, together, formed the indicating blocks--for example LCD elements--so that the shift state of the respective shift register will provide suitable output indications. For example, if a shift register has eight positions, and four sequential positions have a 1-signal and four other sequential positions have a zero-signal, a line can be displayed representative of half-full state of a fuel tank.

Lever switch arrangement for motor vehicle

Abstract: This disclosure is directed to an improved lever switch arrangement for use in a motor vehicle and the like, in which positions of a control lever are clearly indicated through illumination particularly at night for improved operability, while the illumination of the control lever positions is also utilized to display the state of functionings of switch members incorporated in the control lever.

Programmable logic array with test capability in the unprogrammed state

Abstract: A programmable circuit array comprises an input buffer adapted to receive a plurality of input signals for outputting equivalent input signals and inverted input signals. A programmable product array receives the equivalent input signals and the inverted input signals, for generating a plurality of logical product terms. A programmable sum array combines the plurality of product terms to generate a plurality of sum terms, each of the plurality of sum terms being an output of the programmable circuit array. Test logic is included which selectively causes each of the product terms, the equivalent input signals, and the inverted input signals to have a predetermined logic state in response to at least one control signal.

Incrementing/decrementing circuit as for a FIR filter

Abstract: A circuit for incrementing or decrementing a binary number is described. An M bit binary number is applied to M dynamic latch circuits. The latch output signals are applied to M logic units each comprising an exclusive OR, an exclusive NOR and one transistor. The transistors of the respective logic units are connected serially, with the transistor of the logic unit operating on the LSB of the binary number being further connected to a carry in or count signal. The exclusive OR is responsive to the carry in signal and the latched signal to increment/decrement or pass through the respective bit of the binary number. The exclusive NOR is responsive to an Up/Down signal and the latched signal for controlling the conduction state of the respective transistor thereby providing a carry in signal to the input of the next adjacent logic unit operating on the next more significant bit of the binary number.

Monitors as responses to questions: determining competence

Abstract: This paper discusses the application of a propositional temporal logic to determining the competence of a monitor offer as an extended response by a question-answering system. Determining monitor competence involves reasoning about the possibility of some future state given a description of the current state and possible transitions.