Showing papers on "System bus published in 1985"

In-circuit emulator

Abstract: A circuit is disclosed which is implemented on the same silicon chip as a microprocessor to be utilized in a microprocessor system such as a microcontroller, which circuit allows a user to perform in-circuit emulation ("ICE") for the purpose of debugging the microprocessor system. The ICE circuitry comprises (i) capture logic which monitors the contents of the program address register and the internal data bus and various control lines of the processor; (ii) trace circuitry comprising a FIFO buffer which puts data from the capture logic to the output pins of the chip; and (iii) a content addressable memory and a software programmable logic array with emulation counters which together function as a finite state machine which performs the desired predetermined testing of the system.

Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus

Abstract: Disclosed is a multiprocessor computer system including a plurality of processor modules with each of the processor modules including at least one processor and a cache memory which is shared by all of the processors of each processor module. The processor modules are connected to a system bus which comprises independent data, address, vectored interrupt, and control buses. A system memory which is shared by all the processor modules is also connected to the buses, and the cache memories in each processor module store those memory locations in the main memory most frequently accessed by the processors in its module. A system control module controls the operation and interaction of all of the modules and contains the bus arbiters for the vector, data and address buses. The system control module also controls the retrying of requests which are not completed and should any requester fail to obtain access to a bus, the system control module also unjams this deadlock. Each of these multiprocessor computer systems can be connected to another multiprocessor computer system through an interface which includes a cache for housing frequently accessed locations of the other multiprocessor system.

Multicomputer digital processing system

Abstract: A multiple computer digital processing system including several Local Buses positioned orthogonally to a Common Bus. Each Local Bus is connected to the Common Bus through a plugably connected Common Bus interface card to provide a transfer of information between Local Buses across the Common Bus. Computer cards, memory cards and other device cards may be plugably connected to the Local Bus to communicate with each other via the Local Buses and Common Bus. The number and types of cards connected and even the number of Local Buses connected to the Common Bus may be varied according to the requirements of each application. Additionally, the Common Bus includes a shared memory accessible by all devices and an InterComputer Interrupt circuit providing interrupts to the computer cards. Further the computer cards are plugably connectable to a Peripheral Bus to provide communications with peripheral devices located externally to the system. All cards connected to the Local Buses and Common Bus include monitor circuits connected through a Test Bus to a System Monitor that configures the system according to the cards connected and the application requirements, detects errors, monitors performance, and provides fault tolerant repair capability under operator supervision.

Partitioned scan-testing system

Abstract: A test partitionable logic circuit comprises a plurality of functional modules (26a)-(26n). Each of the functional modules is interfaced with the exterior of the logic circuit with a data bus (20), address bus (16) and a control bus (12). Each of the modules (26) is addressable through an address decode/select circuit (52) to operationally isolate the select modules and define a test boundary. Test data is scanned into a serial chain of shift register latches (SRL's) which are connected in a daisy chain configuration. The defined test boundary allows each of the modules to be separately selected and tested such that the test program for an individual module is separate and distinct.

Single-chip microcomputer having a program register for controlling two EEPROM arrays

Abstract: A single-chip microcomputer comprises at least two separate and independent electrically erasable programmable read only memories (EEPROMs) on-board which may be independently programmed, erased and read. Each part of the split EEPROM has its own data bus and address bus. Programming and erasing is controlled by a program register which has separate bits for configuring and latching the data and address buses of a selected EEPROM array, for providing programming voltage to the array of choice and for choosing between programming and erasing the selected array. The split EEPROM provides versatility to the user in allowing one part of the EEPROM to be programmed while the program stored in another part of the EEPROM or RAM may be read and utilized. In addition, test time and effort of the microcomputer may be considerably reduced.

Vehicular data transfer communication system

Abstract: A data transfer communication system capable of handling both node-to-node data transfer messages originating at any transmitter and transmitted to a specific receiver on the network and functional command messages originating at any transmitter and broadcast transmitted to an unspecified number of receivers on the network. Receivers are programmed to receive and acknowledge receipt of correspondingly addressed node-to-node type messages and certain correspondingly addressed functional command type messages with their unique addresses in a predetermined field location of the transmitted message. By utilizing pulse width modulation techniques, binary logic signals and a unique start signal are defined and have a dominant hierarchy that allows for bit-wise contention of the common data bus. In that manner, when contention of the data bus is resolved a higher priority message continues to be transmitted while losing contender delays its transmission until after the higher priority message is completed.

Peripheral controller for coupling data buses having different protocol and transfer rates

Abstract: A peripheral controller is provided for controlling data transfers between peripheral devices operably on one type of data bus to devices operable on a second data bus. An intermediate buffer is utilized so that data is read into one memory block from the sending data bus and read out of another memory block to the receiving data bus. Controls are provided to prevent overwriting data which has not been transmitted and to prevent data transfers from the buffer until at least one block of memory has been filed.

High speed memory system for use with a control bus bearing contiguous segmentially intermixed data read and data write request signals

Abstract: A high speed memory system for 100% bandwidth use with a control bus bearing contiguous sequentially intermixed data read and data write signals including a first buffer for reading data from a storage means into the data bus and a second buffer for writing data from the data bus into the storage means and a memory control sensitive to the order of received write requests and read requests signals to avoid any simultaneous utilization of the data bus and storage means in accordance with a prearranged schedule of preferential utilization of the data bus and storage means. The subject invention and related method further contemplates the employment of a plurality of input/output ports which are responsive to data read and/or data write request signals on the control bus for reading data from and/or writing data into the data bus in synchronism with the utilization of the first and second buffers.

Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion

Abstract: In a cellular array including a matrixed array of processing elements, the processing elements are controlled by software to overcome manufacturing defects, to cooperate together to form words of varying size and to replace cells that become defective during the lifetime of the processor. These cells communicate with memory external to the chip via a time division multiplex bus. The bus is 32-bits wide and each cell is connected to both the upper half and the lower half of the bus. Configuration bits that are loaded into a cell cause communication over the top half or the bottom half of the bus according to the significance of the bits placed in the cells. Words between 16-bits and 246-bits in length may be formed in a case where 20 such cells are implemented on a single chip with four of the cells being deemed to be spare parts. For simplicity, typical word sizes would be 2n×16 bits although in principle any multiple of 16-bits may be obtained. Each cell contains a 16-bit multiport RAM providing general purpose registers for use by the programmer as well as systems registers. The systems registers accommodate the processor status word, a multiplier quotient register, a full-function arithmetic logic unit and path logic to connect the cells together and control the flow of information through the path logic according to the instruction being executed.

Very high-speed digital data bus

Abstract: A time-division multiplexed, data communications system allowing multiple user devices, including super computer buses configured in a local network, and other existing network hierarchies to exchange digital data over extended distances at speeds heretofore unattainable. The system includes a plurality of intelligent nodes, termed "DATApipe™ adapters", which are coupled to a fiber optic bus. The DATApipe adapters function as interface devices between the fiber optic bus and the I/O processors which are used to couple the user devices and networks to the DATApipe adapters.

Resilient bus system

Abstract: A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.

Semiconductor memory device having a serial data input circuit and a serial data output circuit

Abstract: A semiconductor memory device includes a memory cell array (1 a serial data input circuit for high-speed, large data storage in memory cells and a serial data output circuit for high-speed, large data read-out from the memory cells. The serial data input circuit includes a set (15a) of shift registers for consecutively storing serial input data (SIN) applied from an external circuit, and a set (14a) of first gates for simultaneously coupling the shift registers and a plurality of bit lines (BL) of the memory cell array to enter simultaneously the serial input data stored in the shift registers into desired memory cells selected by a desired word line. The serial data output circuit includes a set (12a) of second gates coupled to the bit lines, a set (7a) of data holding circuits, an input of each of which is connectable to the corresponding bit line through the corresponding one of the second gates, a set (11a) of third gates provided between outputs of the data holding circuits and a data bus or buses (26) and for outputting data held in the data holding circuits to the data bus or buses, and a data output circuit (9a, 10a) having a gate driving circuit for selectively driving one of the third gates. The second gates are simultaneously operated to transfer a plurality of data on a selected word line into the data holding circuit set, and the data held in the holding circuits are fed out to the data bus or buses in response to the operation of the third gates. The device can be used for high-speed, large data first-in first-out operation.

Multiprocessor system with standby function

Abstract: A multiprocessor system is comprised of a bus and a plurality of processor modules. Each processor module includes a bus arbitration block, a bus access control block, an address output block, a data input/output block, a clock signal generating block, a stop request block for requesting the stop of supplying a clock signal, an operation processing block for processing data, and a stop control block. The stop control block stores the contents of the bus access (a type of the bus, the address and data concerning the access, etc.) as is made by the operation processing block when the clock signal is stopped, and to what clock of that access cycle the bus access proceeds. The stop control block controls the bus arbitration block to electrically disconnect the processor module from the bus. After the restart of supplying the clock signal, the bus arbitration block, the bus access control block, the address output block and the data input/output block are restored on the basis of the contents of the bus access. Then the bus access that was stopped is resumed from its beginning. When the number of clocks of the clock signal is equal to that stored in the memory block after the restart of supplying the clock signal, the stop control block supplies again the clock signal to the operation processing block. Subsequently, the operation processing block continues the bus access.

Processor I/O and interrupt filters allowing a co-processor to run software unknown to the main processor

Abstract: A co-processor is connectable to a main system data bus to run software unknown to the main processor. The main processor can concurrently run other software and maintains priority over shared I/O facilities by providing trapping logic incorporated in a random access memory and dynamically loadable by the master processor which contains data related to the current useability by the co-processor of a shared I/O device. Additional logic is associated with the co-processor to manage interrupts between the co-processor and the system bus.

Multiple path multiplexed host to network data communication system

Abstract: A data transfer controller allows data to be transferred from a network bus to a system bus in a host computer. The controller has a network bus interface for communicating with the network bus and a system bus interface for communicating with the system bus. The system bus interface has first and second buffers. A dual port memory is utilized and has one port operatively connected to one of the buffers in the system bus interface and to a microprocessor. The direct access channel is established and operatively connected to the other buffer of the system bus interface as well as coupled to the microprocessor and associated control logic. A switch under control of the control logic establishes connections between the second port of the dual port memory and either the direct access channel or the network bus interface.

Microprocessor having variable data width

Abstract: A microprocessor having variable data width comprising a bus cycle changeover circuit between a command execution unit and each of an address output logic, a data input/output logic, and a bus controller. The bus cycle changeover circuit receives an address, data, a memory access instruction and a data width instruction from the command execution unit and modifies timings of them according to an externally supplied data width selection signal and transmits modified address, data, memory access instruction and data width instruction signals to the address output logic, the data input/output logic and the bus controller. The bus cycle changeover circuit comprises a cycle control circuit which outputs a signal expressing a latter half access cycle and an upper/lower selection circuit which selects upper/lower parts of the data bus according to an output signal of the cycle control circuit.

Input/output bus for computer

Abstract: A communication bus (14) provides bidirectional data communication between a computer (12) and various peripheral units including input/output processors (18, 20) and a service processor (22) The computer includes a memory control unit (24) which is connected to a memory array (26) A central processor unit (30) is connected for data exchange with the memory-control unit (24) Data blocks are transferred through the bus (14) and either originate or terminate at the memory array (26) A peripheral unit, such as the processor (18) transfers a data block by first transferring a header parcel (146) which defines an address, block length and type of function This is transmitted to the memory control unit (24) which carries out the desired data transfer by sending or receiving sequential data parcels An interrupt bus (16) connects each of the units of the computer system (10) including the processors (18, 20, 22) and the central processing unit (30) Any one of the units connected to the interrupt bus (16) can interrupt any of the other units The interrupt process comprises sending an interrupt vector through interrupt lines (66) At the receiving unit the interrupt is identified and the appropriate function carried out The combination of the communication bus and the interrupt bus (16) comprises an input/output bus for the computer system (10) to provide a high data bandwidth together with flexible operation

Method and apparatus for bus arbitration in a data processing system

Abstract: In a bus-oriented computer system, the decision as to which unit is to receive the bus takes account of the current status of the bus system and the respective operation to be performed on the bus. For that purpose, status information of the connected units, the bus command to be executed and the address of the requested unit are fed to the allocation logic (arbiter) on separate or commonly used lines, thus avoiding idle times during the use of the bus. By evaluating the bus command, the allocation priority can be dynamically changes in order to suppress bus accesses that are bound to fail from the start.

Logical transform image processor

Abstract: A minicomputer provides signals representative of an image to three memory units via a sixteen bit data bus. Signals representative of sixteen central pixels of the image and neighbors thereof are provided from the memory units to a tessellation memory. In response to the central pixels and their neighbors forming a predetermined pattern, signals representative of the central pixels may be altered, whereby the central pixels are processed simultaneously. Signals representative of the processed central pixels are provided to the minicomputer via the data bus.

Method and arrangement for transmitting data, especially in an aircraft

Abstract: A method and arrangement for the transmission of data, in digital form, in a bus system, which includes a central unit, several stations, as well as a bus line or data bus. During operation, the following different transmission phases take place: An initiation phase, in which the central control unit queries all of the stations and prepares a request phase; the request phase, in which the individual stations report a required bus access; an allocation phase, in which each station obtains a time slot in response to its request; and a data phase, for transmission of the data. The central unit includes a phase control, a request collector, a time slot allocator, and a register. A number of the stations are provided with a request generator in such a way that the latter can signal a need to the bus access. Thus, an optimum utilization of the transmission capacity is achieved, possibly by switching stations off. However, a rapid bus access is possible at any time for important stations.

Multiphase packet switching system.

Abstract: A packet switching system having separate arbitration (110b) and data buses (109a) together with circuitry for dividing the buses into a plurality of time segments termed phases. The plurality of phases permit a like plurality of separate arbitration operations and a like plurality of separate data exchanges to be effected concurrently on the arbitration bus and data bus, respectively. The use of n phases increases the data transmission capability of the system by a factor of n over prior art arrangements using only a single phase.

Single instruction multiple data (SIMD) cellular array processing apparatus employing multiple state logic for coupling to data buses

Abstract: A cellular array having a plurality of processor cells disposed on a chip and interconnected by an internal bus includes data bus couplers for bidirectionally coupling to one or more external buses. The data bus couplers selectively couple buses having multiple logic levels. The number of logic levels on the coupled buses may differ. The internal bus may comprise a plurality of parallel data lines each having two-level logic such as binary data, whereas the external buses may have four-level logic represented by four voltage levels. Each data bus coupler has two-bit A/D and D/A converters parallelly connected to selectively convert two bits of two-level logic data to multiple level data and vice versa. The data bus coupler also has a logic level selector circuit using bidirectional gates for selective operation between buses having similar or dissimilar logic levels. The data bus couplers may be associated with pins organized in a regular architecture and used in connection with bedirectional transceivers to multiplex data corresponding to a multiplicity of external buses onto the internal bus and vice versa. Using this pin architecture the data bus couplers may be dynamically configured to support a collection of two-level and four-level external buses to suit the interfacing needs of the chip.

Test module for asynchronous bus

Abstract: A test module is provided for troubleshooting and diagnosing hardware failures in the interface logic to an asynchronous microprocessor bus at true operating speed until a fault occurs. If a fault is detected, the circuit will halt a microprocessor under test coupled to the asynchronous microprocessor bus and freeze the state of the bus signal lines. The microprocessor under test has bit pattern sets therein. A test microprocessor has test pattern sets stored in internal memory. Test pattern latches are coupled to the test microprocessor for sequentially latching the test pattern sets. Address bus latches and data bus latchs are coupled to the asynchronous bus for latching the state of the address lines as a pattern under test. A comparator is coupled to the asynchronous bus, the test microprocessor, the first means, and the second means, for comparing one of the bit patterns to one of the test patterns wherein a continue signal is supplied to the asynchronous bus and the test microprocessor when the test pattern and the bit pattern are the same so that another of the test patterns and another of the bit patterns may be compared. A diagnose signal is supplied to the test microprocessor when the test pattern and the bit pattern are not the same. Fault latches are coupled to the address bus latches and data bus latches, the test microprocessor, and the asynchronous bus, for outputting the bit pattern when the diagnose signal is generated.

Single-chip microcomputer with internal time-multiplexed address/data/interrupt bus

Abstract: A microcomputer architecture permits communication between a CPU and same-chip ports and input/output circuits to be carried only over a multiplexed address/data/interrupt bus, thereby permitting modified I/O hardware or other circuits to be included in the microcomputer without disturbing the CPU layout.

Digital timeslot and signaling bus in a digital PBX switch

Abstract: A switch in a digital PBX system supporting both centralized and distributed switching techniques. The switch has nearly universal parallel bus (10) between line card modules. The bus having a timeslot bus capable of having more than one line card module connected to it, which may communicate voice PCM or data signals during one timeslot. The bus (10) also has a signalling bus (26, 27, 28, 29) by which line card modules are selected to communicate with a central control module by a single line to maintain the universality of the bus (10). Signalling information is also passed between a selected line card module and the central control module by a pair of parallel lines (27, 28).

Distributed bus arbitration for a multiprocessor system

Abstract: A computer system has a plurality of processors sharing a bus. Bus arbitration circuitry is located on each processor for determining bus access. The identity of the processor which is responsible for arbitrating bus access changes from time to time. Each processor has a plurality of possible arbitration states, which are controllable through execution of software by the processor.

Memory bank switching apparatus

Abstract: A memory bank switching apparatus equipped with a bank switching register, wherein a specific address signal within a prescribed address scope for access to ROMs is outputted onto an address bus, and data relative to the address of a memory bank to be used subsequently is outputted onto a data bus, so that a location in the bank switching register is selected by the address signal. Then the data on the data bus is written in the bank switching register, thereby enabling only the memory bank selected according to the content of the bank switching register.

Serial bus system and method for selection of bus subscribers

Abstract: In a serial bus system an active representation of the logic states of a bus signal for transmission of both logic states is implemented either on two separate lines for separate transmission of the logic states thereon or on a single line with both logic states being represented by different frequencies. In the method selection of a subscriber connected to the bus, the subscribers wishing to transmit a message indicate this by issuing a collision signal to the bus. The time period during which the collision signal is issued by each subscriber is chosen in such a way that each subscriber of the bus has the possibility to be prepared for the selection. The selection of the subscriber wishing to transmit a message then is done by means of an address comparison on a bit-by-bit basis.

Synchronous/asynchronous communication system

Abstract: A data bus system includes a plurality of serially connected active terminals configured to receive data and either retransmit the received data or transmit new data to the next adjacent terminal. The terminals are configured in a diagnostic mode to configure the system optimally at turn-on or in the event system faults occur, and are configured in a user access mode once optimum configuration is attained. The system is under control by one terminal at any one time during the diagnostic mode and any terminal is capable of being the control terminal. For operation in the user access mode a cyclic period is defined during which a portion of the period is set aside for synchronous transmissions and another portion of the period is set aside for asynchronous transmissions. Both synchronous and asynchronous users are thereby accommodated by the bus.

System for controlling access to computer bus having address phase and data phase by prolonging the generation of request signal

Abstract: A computing system is disclosed which uses a system busy signal on its system bus to help control access to said bus. One or more requesters can generate a request signal when the system busy signal is not asserted. System busy is asserted along with the request signal(s) and remains asserted until all requesters which generated a request signal have gained access to the bus in order of priority. A freeze signal is generated on the system bus during the address phase of an instruction and a wait signal is generated during each data transfer in the data phase of an instruction. The freeze signal may be generated by a memory control unit, a memory module or a requester.