Showing papers on "System bus published in 1992"

Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

Method and apparatus for automatically configuring a computer peripheral

Abstract: A host computer, coupled to a peripheral device by its system bus, identifies an available input/output address and designates that input/output address as being assigned to that peripheral device. After identification of the available input/output address, the host computer transmits a logic trigger signal in the form of a sequence of write commands that write the assigned input/output address, as well as other configuration parameters, to an infrequently used input/output address. In response to the logic trigger, the peripheral reads and stores the assigned input/output address and other configuration parameters from the host computer's data bus, The configuration parameters and the assigned input/output address are then written to an EEPROM for non-volatile storage. After this configuration is established, the peripheral device automatically retrieves the stores configuration parameters and assigned input/output address from the EEPROM every time the host computer is turned on or is otherwise reset.

Vehicle proximity sensor

Abstract: A vehicle sensing system includes a data bus, a first microprocessor coupled to the bus and a plurality of sensor modules about a vehicle periphery for detecting the presence of objects within a predetermined range of distances of each of such sensor modules. Each sensor module of the vehicle sensing system includes a transducer, a second microprocessor, coupled between the transducer and the bus, for processing information received from the transducer, and a light emitting diode disposed on an outer surface of a housing for the transducer, coupled to the second microprocessor, for indicating when an object is within the predetermined distance of the sensor module or when the sensor module is faulty. Each sensor module further includes a temperature sensing circuit coupled to the second microprocessor and a bus transceiver for receiving information from the bus and for transmitting information to the bus.

Secure computer system having privileged and unprivileged memories

Abstract: The microprocessor resides along with its protected real address space in a secure module surrounded by tamper resistant circuitry pad. Encryption programs and encryption keys are stored in the protected memory. A second real address space is also connected to the address and data bus of the microprocessor in order to provide program and data space for a user. Gating circuitry prevent the exposure of instructions and data form the privileged memory from appearing outside of the secure module. The gating circuits switch address spaces by recognizing a sequence of predetermined addresses.

Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority

Abstract: A multiprocessor type time varying image encoding system having a plurality of digital signal processor (DSP) modules (DMM's) connected in parallel, each DMM having a DSP, a local memory and an interrupt control unit, a plurality of common memories for storing data which is being processed, parameters, etc., an input frame memory which enables reading and writing operations to be executed asynchronously, a combination of a task control unit and a task table for distributing tasks to the DMM's, a plurality of independent common buses, and a combination of a bus control unit and a bus control table for bus sharing control.

Apparatus for insuring the security of output signals from protective relays used in electric power systems

Abstract: In a protective relay (10), which contains a microprocessor (30), for monitoring a power transmission line, an output enable decoder (72) and a one-shot timer (74) produce a very short (5 microsecond) signal in response to an address signal from the microprocessor. The output from the timer is applied as one input to AND gate (70). A conventional address decoder, responsive to an address signal identifying a particular output port from the microprocessor, provides another output to AND gate (70). AND gate (70) produces a latch control signal when the two signals are coincident in time. The latch control signal enables the particular output port to receive instructions from a data bus (60).

Methods and apparatus for bus access arbitration of nodes organized into acyclic directed graph by cyclic token passing and alternatively propagating request to root node and grant signal to the child node

Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node

Shared bus in-circuit emulator system and method

Abstract: An in-circuit emulator, alternatively referred to as a microcontroller debugging system, has a control processor having I/O ports and a multiplexed address/data bus port, an emulation processor having I/O ports and a multiplexed address/data bus port, an emulation memory having address inputs, a data bus interface and a plurality of two-to-one multiplexers. The in-circuit emulator is configured such that the control processor and the emulation processor each have at least one port directly coupled to the data bus of the emulation memory without the use of external tri-state buffers, this is referred to as the shared bus. An address latch, shared by both processors, has its inputs coupled to the shared bus. The outputs of the address latch form a portion of the emulation memory address input, and are coupled to a corresponding portion of the emulation memory address inputs. The emulation processor is supplied with a clock which is selected from the group consisting of: the same clock input signal used by the control processor, a clock synchronized with the internal clock of the control processor and a clock which is asynchronous with respect to the internal clock of the control processor.

Bus-oriented switching system for asynchronous transfer mode

Abstract: A local network system is provided using ATM-like framing and cells for data transmission. A bus architecture is defined, making the cost per port relatively low compared to matrix switching. For high performance, the bus is bit parallel instead of being a serial link. Like other LANs, the average bandwidth per interface (per port) is a low percentage of the peak bandwidth. A single physical bus is used to interconnect a potentially large number of ATM interfaces, on the order of hundreds. The system employs a bus master which provides timing and resolves all arbitration requests. Interfaces connected to the bus are allotted at least one cell per frame for sending data, and write to the allotted cell in synchronization with the frame, cell and bit clocks circulated on the bus from the master. There are more cells than interfaces, so when an interface has a large data block to send it asks for allocation of more cells per frame, and the request is granted by the master coordinated with other demands on the system. This bus arrangement allows construction of a switching system providing asynchronous transfer mode (ATM) cell switching with an aggregate throughput defined by the bus transfer speed, potentially in the multi-gigabit range, while also allowing the bus to be used for pre-arbitrated (isochronous) transmission. The bus uses a "traveling wave" technique to allow arbitrary physical length (many times the transit distance of one bus cycle) while using a simple, lower-speed sub-bus for bandwidth arbitration.

Data processor with bus-sizing function

Abstract: A data processor capable of controlling memory accessing by the same controls regardless of the bus width to be used. A register is provided for storing data to be inputted and completing a block of data with a size equal to that of the whole bus width of the external data bus when the microprocessor accesses external memory by using only a part of the bus width of an external data bus according to a bus-sizing function. A bus interface is provided for starting memory access by dividing a bus cycle into plural portions according to the bus width and for controlling operation so as to access data equal in size to the case where the whole bus width of the external data bus is used for accessing.

Modular mother satellite bus for subsidiary payloads

Abstract: Multiple subsidiary small payloads are connected to standard mechanical and electrical interfaces provided by an expendable or recoverable modular mother satellite bus (MMSB) and launched into space as an assembly acting as a common carrier providing low unit launch costs for the attached subsidiary payloads and also providing a variety of electrical, pointing, and thermal control services for these payloads after reaching orbit. These services include but are not necessarily limited to controlled separation of free-flying satellites or re-entry vehicles, regulated electric power at a variety of voltages, telemetry, computer control, payload control via time delayed pre-programmed instructions, optional real-time payload control via direct radio communication or transmission through geostationary or other communication satellite links, time-driven or event-driven control logic, mass data memory, encryption and decryption of data and commands, payload pointing, augmented heat rejection, and interconnection between subsidiary attached payloads through the data bus.

Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode

Abstract: An interface circuit is described for interfacing a peripheral device and a microprocessor to enable data transference between a memory location within the peripheral device and a data bus of the microprocessor. In accordance with the type of bus control used by the microprocessor, the interface circuit is operated in either a synchronous mode or an asynchronous mode. The interface includes a state machine that responds to the mode of interface operation, a clock signal provided by the microprocessor, requests from the microprocessor to access an addressed peripheral memory location, and a busy signal from the peripheral device indicating when the peripheral is engaged in transferring data between the interface circuit and an addressed peripheral memory location. Preferably, the interface also operates to detect error conditions based on changes in the access request during data transference between the microprocessor and the peripheral device. In response to detecting an error condition, the state machine acts to interrupt data transference to avoid the transfer of invalid data.

Programmable priority arbiter

Abstract: The present invention is directed to a programmable logic circuit used as an arbiter to control access to a shared resource, eg a system bus, by N devices in a computer system The programmable arbiter according to the present invention, implements a logic design with sufficient flexibility to accommodate and selectively incorporate features of several different arbitration schemes including a straight priority scheme, a programmable arbitration, and a rotating priority arbitration scheme In addition to these arbitration schemes, the arbiter of the present invention supports an extended programmable arbitration scheme whereby a device which is requesting access to the shared resource may be granted access to the resource even if it has used up its allocated share of bandwidth if there are no other devices requesting access to the shared resource Furthermore, bus bandwidth may be allocated to particular device or to a group of devices at a particular priority level In addition to providing for programmable allocation of bus bandwidth, the arbiter of the present invention permits the number of clock cycles allocated per bus window for one requesting device to be different from the number of clock cycles allocated per bus window for another device In this manner, the size of the bus window can be designed to accommodate the individual requirements of each device permitting maximization of both the device's and the system's overall efficiency

Method of arbitration for buses operating at different speeds

Abstract: In a bus adapter coupling a system bus and an I/O bus which operate at different speeds and contain a plurality of devices, a method by which an arbiter in the bus adapter prevents contention for ownership of both buses by a device on either of the buses. The method includes the steps of sampling each of the devices requesting ownership of said buses and asserting a bus grant to one of the devices on one of the buses based on its assigned priority number. The method also includes the step of waiting for the device granted the bus to send an acknowledge signal to display ownership of the buses and for each of the devices not on the bus containing the device granted the bus to see the acknowledge signal before resampling and reasserting a new bus grant to another of the requesting devices.

A bus on a diet-the serial bus alternative-an introduction to the P1394 High Performance Serial Bus

Abstract: The author discusses the justifications for the use of a serial bus in computer systems. He then describes a leading proposal for such an interconnect: the IEEE P1394 High Performance Serial Bus. The highlights of the Serial Bus include: (1) a physical layer supporting both cable media and many ANSI/IEEE standard 32-bit buses; (2) variable speed data transmission with a base speed of almost 100 Mbit/sec between nodes separated by distances up to 10 meters; (3) both fair and priority arbitration mechanisms with all nodes guaranteed at least partial access to the bus regardless of priority; (4) bus transactions that include block and single quadlet reads and writes, as well as an isochronous mode which provides a low-overhead guaranteed bandwidth service; and (5) dynamic address assignment that does not require switches or a physical 'slot number'. >

Method and apparatus for transferring data in portable image processing system

Abstract: A microprocessor system, including a central processing unit (CPU), data source device and data destination device electrically interconnected by first data bus lines, address bus lines and control bus lines of a system bus, is implemented with a transfer signal control line, and second data bus lines interconnecting the data source and data destination devices for direct background transfer of data between the devices. At least one of the devices includes individually sequentially addressable storage locations, and associated address and count registers. The data source device includes "ready" and "enable output" terminals, and the data destination device includes "ready" and "enable input" terminals, all connected in AND-gate configuration so that the devices are enabled for data transfer through the second data bus lines only when both device "ready" signals and the transfer control signal are all present. A starting address is loaded in the address register and a total data unit count is loaded in the count register using the first data bus lines. The transfer control signal is then given, with the address and count registers incremented after each data unit is transferred. Once the process is started, data is transferred data unit-by-data unit and without the need for direct CPU involvement, in synchronism with the system clock, until the count register indicates completion of transfer of the entire block.

SCSI interface employing bus extender and auxiliary bus

Abstract: A bus interface employs a bus extender for connecting an auxiliary bus to a single port on a main bus in such a way as to interconnect one or more host computers on the main bus to one or more peripheral devices on the auxiliary bus. The bus extender employs a transceiver coupled to the main bus, another coupled to the auxiliary bus, and signal transfer and logic circuitry passing signals between and controlling the operation of the transceivers. The circuitry also performs all address translation necessary for inter-bus communication. Once communication links have been established with the designated devices on the other bus, the extender sends message data signals received over the one bus directly onto the other bus without modification. Since the interface can comply with SCSI standards, any of a variety of types of commercially available peripheral devices having controllers complying with those standards can be supported on the auxiliary bus.

System for switching between two different operating systems by invoking the server to determine physical conditions to initiate a physical connection transparent to the user

Abstract: A hybrid system environment includes a proprietary operating system and processing unit and a non-proprietary operating system (UNIX based) and processing unit. The systems tightly couple to a system bus in common with a main memory and a number of multiline communications controllers and communicate through a common area of main memory. The UNIX terminal connections to such controllers are virtual connections applied by a virtual terminal driver through the system proprietary communications software components. These components include a server, a network terminal driver (NTD) and a number of multiplexer driver modules. A multiplexer physical terminal driver is included in the UNIX-based operating system and a switching mechanism is incorporated into the virtual terminal driver for enabling switching to such physical terminal driver when a user switches via a switch command to the UNIX-based operating system. The server module upon being invoked upon such switching operates to establish a direct communications path between an application running under the UNIX-based operating system and the controller communications line paths through the multiplexer driver module and logically disconnects the virtual communications line path from the NTD module to the multiplexer driver module thereby improving system efficiency and terminal connectivity.

Computer system with a processor-direct universal bus connector and interchangeable bus translator

Abstract: A universal processor-direct bus structure on a specifically partitioned motherboard uses a separate local bus translator card to adapt to a specific local bus protocol and configuration The processor-direct bus on the motherboard contains a superset of all of the primary signals required to implement any desired local bus structure The translator card incorporates the connectors and bus translation protocol for a specific local bus structure on a separate card which is connected to the partitioned motherboard through the universal processor-direct bus Thus, the universal processor-direct bus combined with the translator card makes it possible to have a standard bus (for example an ISA (Industry Standard Architecture) bus, EISA bus, MCA bus, PCI bus, C-bus, S-100 bus and/or other buses) mounted directly on the motherboard with one or more of the same standard buses or a different local bus interfaced to the motherboard through the universal processor-direct bus This unique combination of a motherboard having a universal processor-direct bus with plug in local bus translator cards provides a unique, low cost, flexible solution to the problem of standard and local bus obsolescence, local bus non-upgradeability and local bus non-flexibility

Method and apparatus for concurrency of bus operations

Abstract: A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.

System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)×(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Bus interface logic for computer system having dual bus architecture

Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.

Interface for use with a process instrumentation system

Abstract: The present invention relates to an interface for a maintenance system used in conjunction with a process instrumentation system. More specifically, the invention relates to an interface used for maintaining and configuring smart devices. Even more specifically, the invention relates to an interface that may safely be used to maintain and configure smart devices where such smart devices are located in hazardous areas. The interface, which may be removably mounted to a termination board, has a control section, a port replacement section, a permanent storage section, a temporary storage section, an address/data bus, a UART, a standard clock pulse generation device, an option select device, a modem, a channel selection decoder, a wave shaping device, and at least one multiplexer. The interface and a termination board for use in process instrumentation systems that require intrinsic safety are explained by themselves and in system and function contexts.

SIMD architecture with transfer register or value source circuitry connected to bus

Abstract: A SIMD parallel processor includes two types of circuitry interconnecting its processing units: One kind interconnects the processing units into an array so that each processing unit can transfer data to an adjacent processing unit in the array and can receive data from an adjacent processing unit; the processing units can, for example, be interconnected in a one-dimensional array. Another kind of interconnecting circuitry includes bus circuitry to permit greater freedom in transferring data to and from processing units. Connected to the bus is a register, so that data can be transferred between processing units by first transferring data from one processing unit to the register and by then transferring data from the register to another processing unit. Or data stored in the register can be sent to a subset or to all of the processing units. Similarly, control circuitry can itself provide data on the bus for transfer to one, a subset, or all of the processing units. A bidirectional register can be connected between each processing unit and the bus, so that a processing unit can be selected to provide data to the bus by selecting its bidirectional register. Similarly, each processing unit can include a memory that can be selected with a write enable signal so that a set of processing units can be selected to receive and store in memory data from the bus.

Method of implementing a neural network on a digital computer

Abstract: A digital computer architecture specifically tailored for implementing a neural network. Several simultaneously operable processors (10) each have their own local memory (17) for storing weight and connectivity information corresponding to nodes of the neural network whose output values will be calculated by said processor (10). A global memory (55,56) is coupled to each of the processors (10) via a common data bus (30). Output values corresponding to a first layer of the neural network are broadcast from the global memory (55,56) into each of the processors (10). The processors (10) calculate output values for a set of nodes of the next higher-ordered layer of the neural network. Said newly-calculated output values are broadcast from each processor (10) to the global memory (55,56) and to all the other processors (10), which use the output values as a head start in calculating a new set of output values corresponding to the next layer of the neural network.

Automatic signal termination system for a computer bus

Abstract: An automatic termination system for an end terminated bus especially useful with the SCSI bus. When utilized with a computer device, for example, a storage subsystem, configuration or reconfiguration of the bus can be automatically effectuated without concerns for inappropriate signal termination of the bus. The invention comprises a circuit which determines if any additional devices have been coupled to the bus and enables an active terminator chip if none is detected. Should another device be coupled onto the bus, the active terminator chip is automatically disabled.

Tri state buffer circuit for dual power system

Abstract: A CMOS tri-state buffer circuit transfers digital signals between a first digital circuit system operating at 3.3 Volts and a second system operating at 5 Volts. The buffer circuit receives an active high enable signal and a data signal as inputs to a tri-state select network. When the enable signal is high, data is propagated through a driver stage and onto a data bus in the second system. Driver clamp circuitry and an n-well voltage controller operate conjunction with the driver stage to prevent the 5 volt supply of the second system from interfering with the circuitry of the of the 3.3 Volt system. A clamped line driver transmits signals from the 5 Volt system to the 3.3 Volt system.

Apparatus and method of data transfer between systems using different clocks

Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device. In accordance with a further aspect of the invention, an apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

High-density double-sided multi-string memory module with resistor for insertion detection

Abstract: A high-density memory module has thirty-two memory integrated circuit chips, sixteen decoupling capacitors, and two resistors mounted on a double-sided multi-layer printed wiring board having a series of edge terminals for connection to a motherboard. One side of the board has a first 2×8 rectangular matrix of the chips, and the other side of the board has a second 2×8 matrix of the chips. The chips are grouped into four "strings," each of which includes eight chips which receive the same row address strobe and column address strobe. Each string is selected by a unique row address strobe. All four strings share a common data bus. Two of the strings share a first column address strobe and a first address bus, and the other two strings share a second column address strobe and a second address bus, to facilitate four-way interleaved memory access. Address, data, power, and ground terminals are distributed and dispersed along the series of edge terminals, but terminals for one address bus is disposed between a first half and a second half of the terminals for the other address bus. One of the two resistors is used for indicating the type of the memory chips in the memory module, and the other resistor is interconnected with similar resistors in other memory modules on the motherboard to provide a combined resistance indicating the number of memory modules on the motherboard.

High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous bank pointers to specify a return bank

Abstract: A processor includes a bank-structured memory and is capable of handling multiple interrupts. The processor includes a central processing unit (CPU) comprising a plurality of data memories serving as general-purpose registers, and a plurality of bank specifying registers for use in specifying an address to save and restore data without involving an external system bus which connects the CPU and a program memory, such as a built-in read only memory (ROM), for storing a user program. The processor further includes a bank structured memory, connected to the CPU via an exclusive-use data bus, for holding data stored in the data memories using the bank specifying registers and for returning data stored in the bank structural memory to the data memories using the bank specifying registers. The bank specifying registers include a current bank pointer (CBP) or register for indicating a position of a bank presently in use, and a previous bank pointer (PBP) or register for indicating a bank position of data to be returned to the data memories after completing an interrupt routine. The processor may also include a program counter (PC) for indicating an address of a next instruction to be executed by the processor, a processor status word (PSW) for indicating a status of the processor, and a user stack pointer (USP) for indicating an address of a bank storing values of the program counter.