Showing papers on "Thin-film transistor published in 1972"

Schottky barrier type field effect transistor

Abstract: A Schottky barrier gate field effect transistor is capable of operating in the enhancement mode. The transistor includes a gallium arsenide layer formed on a substrate. The relationship between the thickness W and impurity concentration N of the gallium arsenide layer is given by the expression: 2 X 103CM 1/2 < W . square root N < 3 X 103 cm 1/2.

Pocketable direct current electroluminescent display device addressed by mos and mnos circuitry

Abstract: A small, pocket size, direct current flat electroluminescent display panel made of a single crystalline substrate having electroluminescent material on the front face and addressing circuitry on the back face. The addressing circuitry is conductively connected to the electroluminescent material through feedthrough holes in the substrate. The feedthrough holes are produced by electrons beams or laser beams, or by photo-etching techniques. The addressing circuitry may be, for example, metallic oxide semiconductors or thin film transistors. A large scale integrated thin film transistor circuit could be deposited into a matrix, from a multiple of evaporation sources, through a system of registered masks positioned on the back side of the substrate. The electroluminescent material may comprise a matrix of light emitting diodes, or alternatively a solid sheet of Group II-VI heterojunction sandwich structure. The matrix of light emitting diodes may be made of gallium arsenide phosphide materials that are in exact registration with the addressing circuitry and connected thereto by conductors connected through the feedthrough holes. Voltage pulses from shift registers in a predetermined pattern are applied to the matrix of addressing circuitry. Outputs from the addressing circuitry cause the electroluminescent material that is conductively connected thereto to conduct, providing a display in the predetermined pattern of the voltage pulses from the shift registers.

Variable capacitance device

Abstract: This specification discloses variable capacitance devices which vary their capacitances under the influence of DC bias voltages or radiations. One embodiment comprises a PN junction diode, a dielectric thin film deposited on the surface of said junction diode at which the junction terminates and a conducting electrode deposited on the dielectric thin film, in which the area of an equivalent plate electrode formed in said junction diode is varied by changing the thickness of a depletion region. In another embodiment, a nonlinear resistance layer deposited on the dielectric thin film is employed. As a DC voltage as applied to the nonlinear resistance layer is increased, the lateral conductivity of the nonlinear resistance layer increases and the area of the equivalent plate electrode facing the conducting electrode is increased. A further embodiment employs a thin film transistor or a MIS transistor to vary the area of the equivalent plate electrode provided therein.

Semiconductor device and the method of making the same

Abstract: A semiconductor device comprising a p type semiconductor substrate including an n channel depletion mode metal-oxide-semiconductor field effect transistor provided with a gate insulating double layer formed of a silicon oxide layer and a phosphosilicate glass layer and an n channel enhancement mode metal-oxide-semiconductor field effect transistor provided with a gate insulating double layer formed of a silicon oxide layer and an alumina layer, the portions of the semiconductor substrate other than those where the field effect transistors are formed being provided with a double layer of a silicon oxide layer and an alumina layer, or of an alumina layer and a phosphosilicate glass layer.

Polarizability of a Bias–Temperature Drifted Species in Thin Film Transistor Structures

Abstract: Instabilities in thin film transistors have been observed and it has been possible to isolate each instability in samples and study its effect separately. An instability involving the trapping and ...

Process for the formation of selfaligned silicon and aluminum gates

Abstract: A PROCESS FOR THE SIMULTANEOUS FORMATION OF SELFALIGNED SILICON GATES AND ALUMINUM GATES HAVING SELFALIGNED CHANNEL REGIONS ON THE SAME WAFER IS DISCLOSED. BASICALLY, THE PROCESS CONSISTS OF THE DEPOSITION OF SUCCESSIVE LAYERS OF SILICON NITRIDE AND POLYCRYSTALLINE SILICON OVER THICK AND THIN SILICON DIOXIDE REGIONS WHICH ARE DISPOSED ON THE SURFACE OF A SEMICONDUCTOR WAFER. POLYSILICON GATES ARE DELINEATED IN THE THIN OXIDE REGIONS. SUBSEQUENTLY, A CHEMICALLY VAPOR DEPOSITED SILICON DIOXIDE LAYER IS FORMED OVER THE SURFACE OF THE EXPOSED SILICON NITRIDE LAYER AND OVER THE POLYCRYSTALLINE SILICON GATE GEGIONS. AT THIS POINT, THE CVD OXIDE IS DELINEATED TO FORM AN OXIDE MASK WHICH WILL PERMIT THE REMOVAL OF SILICON NITRIDE DOWN TO THE THIN OXIDE AT CERTAIN REGIONS WHERE DIFFUSION WINDOWS ARE TO BE FORMED IN EXPOSED THIN OXIDE REGIONS WHICH ARE SUBSEQUENTLY REMOVED BY A DIP ETCH. WHILE THE EXPOSED THIN OXIDE REGIONS ARE MASKED BY EITHER SILICON NITRIDE PORTIONS OR POLYCRYSTALLINE SILICON GATE REGIONS, THE MASKING REGIONS OF CVD OXIDE WHICH PROTECTED THE SILICON NITRIDE LAYER ARE SIMULTANEOUSLY REMOVED BY THE DIP ETCH WHICH OPENS THE DIFFUSION WINDOWS IN THE THIN OXIDE REGIONS. AFTER A DIFFUSION STEP WHICH INCLUDES DEPOSITION OF A PHOSPHORUS DOPANT IN THE DIFFUSION WINDOWS FROM THE VAPOROUS PHASE AND A DRIVE-IN STEP, A THERMAL OXIDATION STEP IS CARRIED OUT WHICH COVERS THE DIFFUSED WINDOW REGIONS AND THE POLYSILICON GATES AND THICK OXIDE REGIONS LEAVING THE EXPOSED NITRIDE PORTIONS UNAFFECTED. IN A SUBSEQUENT MASKING STEP, DIFFUSION CONTACT WINDOWS AND SILICON GATES CONTACT WINDOWS ARE OPENED. THEN, METALLIZATION IS DEPOSITED EVERYWHERE AND DELINEATED TO FORM METAL GATES AND CONTACTS TO BOTH DIFFUSIONS AND SILICON GATES. METAL IS DELINEATED AND FORMED IN EACH OF THE EXPOSED SILICON NITRIDE REGIONS ONE OF WHICH IS A SELF-ALIGNED CHANNEL REGION FOR A METAL GATE FIELD-EFFECT TRANSISTOR. OTHER METAL GATES FOR A CHARGE COUPLED DEVICE ARE POSITIONED BY VIRTUE OF THE PRESENCE OF ADJACENT POLYSILICON GATES AND ARE INSULATED FROM THE SUBSTRATE BY A THIN OXIDE AND NITRIDE LAYER AND FROM THE SILICON GATES BY A LAYER OF THERMALLY GROWN SILICON DIOXIDE ON THE SURFACE OF THE SILICON GATES. THE RESULTING STRUCTURE INCLUDES A METAL GATE FIELD-EFFECT TRANSISTOR, A SELF-ALIGNED SILICON GATE FIELD-EFFECT TRANSISTOR, AND A CHARGE COUPLED DEVICE ON THE SAME WAFER. BY USING AN ADDITIONAL MASKING STEP OVER THAT REQUIRED FOR THE FORMATION OF SILICON SELF-ALIGNED GATES ALONE, METAL GATES WHICH ARE EITHER SELF-ALIGNED BY VIRTUE OF ADJACENT POLYSILICON GATES OR BY VIRTUE OF THE PRESENCE OF A SELF-ALIGNED CHANNEL ARE THUS OBTAINED. IN ADDITION, A RANDOM ACCESS CHARGE COUPLED DEVICE WHICH INCORPORATES A METAL TRANSFER GATE AND A POLYSILICON STORAGE PLATE IS ALSO DISCLOSED. THE STRUCTURE RESULTS FROM THE ABOVE DESCRIBED FABRICATION PROCESS AND IS STRUCTURALLY UNIQUE IN THAT THE METAL GATE IS DISPOSED IMMEDIATELY ADJACENT TO A DIFFUSION REGION WHICH ITSELF IS DISPOSED UNDER A THICK OXIDE LAYER. IN ADDITION, THE POLYCRYSTALLINE SILICON STORAGE PLATE IS SPACED FROM THE METAL GATE BY A LAYER OF THERMALLY GROWN SILICON DIOXIDE.

Coplanar-electrode thin-film InSb transistor

Abstract: A thin-film transistor, using very thin flash-evaporated and annealed InSb films as semiconductor in a coplanar-electrode structure, is characterized by a relatively large transconductance and a well-defined saturation region.

Influence of polycrystallinity on transconductance of thin-film transistor

Abstract: A comparison between the transconductances of polycrystalline and monocrystalline TFT's and the relation for optimal grain size with regard to the TFT transconductance are presented.