Showing papers on "Thin-film transistor published in 1973"

Process for fabricating MNOS non-volatile memories

Abstract: The switching speed of an MNOS field effect transistor is increased by a heat treatment in an ammonia rich atmosphere during processing. The transistor has an insulated gate structure comprising a layer of silicon nitride deposited on a layer of silicon oxide. After the formation of the silicon oxide layer and immediately prior to the formation of the silicon nitride layer on a surface thereof, the surface of the silicon oxide layer is heat treated in an ammonia enriched atmosphere to remove substantially all remaining oxygen atoms and molecules absorbed on the surface.

Method for making FET circuits

Abstract: An integrated circuit and process for manufacturing same is disclosed. The integrated circuit comprises both depletion and enhancement mode field effect transistors, each having silicon gates and self-aligned gate regions. The process includes forming a thick oxide layer on the substrate, removing the thick oxide at the transistor sites, forming a thin oxide at the transistor sites, masking selected transistor sites to selectively implant ions at the other sites, depositing a polysilicon layer over the slice and patterning the polysilicon layer to form gate electrodes, removing the thin oxide using the polysilicon gate electrodes as masks, diffusing the source and drain regions, forming an insulating oxide, then applying the source drain and gate contacts and interconnects.

Method of forming self-aligned field effect transistor and charge-coupled device

Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

Tunnel transistor

Abstract: A tunnel transistor which can be easily obtained by the conventional silicon planar technology will be proposed. It promises fine control of electrical characteristics and high yield. The yield per one wafer in the wafer checking has amounted to 100 percent.

Electrical Properties of Evaporated Tellurium Films and TFT's

Abstract: In situ measurement of the resistivity of p-type Tellurium films (thickness≃150 A) as a function of deposition rate has been made for evaluating their strain sensitivity and incorporation into TFT's. Films deposited at 2 A/sec and subjected to an elongation strain displayed a small strain induced resistivity change which switched from a negative to a positive value as the voltage was increased. For all higher rates, the film showed a consistently positive effect regardless of the applied voltage. The anomalous behavior is ascribed to the conditions affecting the barrier height as the grain boundaries. Exposure to air generally resulted in a marked increase in conductivity. No significant increase in the strain sensitivity was observed in a transistor device using SiO and Al as the insulator and gate electrode respectively although the gate voltage modulation of the drain current was quite normal.

Process for the production of high value ohmic load resistors and mos transistors having a low starting voltage

Abstract: In a process for the production of circuits having at least one field effect transistor including a source, a drain, and a gate electrode, and having a resistor on a common substrate in which, starting with a substrate body having at least one field effect transistor, the process includes the formation of an enhancement type field effect transistor by ion implantation in the channel to decrease the starting voltage and the formation of the resistor by ion implantation adjacent the field effect transistor, wherein the resistor has a value which is high in comparison with the forward resistance of the conductive field effect transistor and low in comparison with the reverse resistance of the field effect transistor.

Method for production of p-channel field effect transistors and product resulting therefrom

Abstract: A process for the production of a p-channel field effect transistor in a semiconductor layer of silicon disposed on a spinel substrate which includes the step of annealing the substrate as well as the silicon in a hydrogen atmosphere after the formation of the transistor has been completed. The formation of the electrodes and conductors for the field effect transistor may take place either before or after the annealing of the substrate and the silicon.

Method for improving the radiation resistance of silicon transistors

Abstract: A method for improving the radiation resistance of silicon transistors of the type having silicon oxide cover layer in which a transistor or a silicon wafer with several transistor structures therein is exposed to electron radiation with an energy below 150 keV for a dose of between 109 and 1010 rad at the boundary layer between the silicon and the silicon oxide cover layer while being at a temperature of between 200 DEG and 300 DEG C. After the irradiation the transistor or silicon wafer is annealed for at least 10 hours at a temperature of between 200 DEG and 300 DEG C while a voltage of at least 0.3 V is applied in the forward direction between the emitter and the base terminal of the transistor or the transistor structures.

Semiconductor device with isolated circuit elements

Abstract: An integrated circuit comprising at least an insulated transistor which is connected to a transistor, the circuit elements being provided in a surface layer of a semiconductor device which is present on a base layer or substrate of the same one conductivity type and has a lower resistivity. The insulated transistor is present within a cup-shaped insulation zone of the opposite conductivity type. The said resistor is at least partly formed by the lateral resistor in the surface layer between the active part of the transistor and an aperture in the insulation zone through which the resistor is electrically connected to the substrate.

Strain sensitivity of thin-film InSb transistor

Abstract: A thin-film InSb transistor with well-defined saturation at room temperature exhibits useful strain sensitivities.

Thin Film Display Switches.

Abstract: : A thin film transistor with a floating second gate, capable of nonvolatile storage of analog data, was the subject of the investigation. Further development resulted in a closely controlled, reproducible fabriacation process and a higher voltage capability. A 40x40 element, 1 inch square matrix, consisting of X-Y addressible memory transistors at each point was designed, laid out using CAD techniques and fabricated in a single vacuum deposition cycle. Mask and substrate registration techniques were also improved, resulting an excellent run-to-run reproducibility of the deposition patterns. By coating the finished memory matrices with an electroluminescent phosphor (Westinghouse 'hypermaintenance' phosphor), providing a common transparent front electrode and sealing with a cover-glass, complete 40 x 40 element storage displays were made. The displays were operable up to 140V peak-to-peak. The EL driving frequencies ranged from 3 to 20 kHz. Writing of information into individual elements was demonstrated by (manual) pulsing of rows and columns. Letters were written into the panel in this manner, and the non-volatile storage of such patterns over periods of excess of 90 minutes was demonstrated.