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Showing papers on "Topology (electrical circuits) published in 1979"


Journal ArticleDOI
TL;DR: In this article, two closely related, low-sensitivity, active switched capacitor fitter topologies are presented, which are immune to the various parasitic capacitances normally present in switched capacitor networks.
Abstract: Two closely related, low-sensitivity, active switched capacitor fitter topologies are presented. Each of these circuits comprises two operational amplifiers and at most nine capacitors. The topologies have been carefully constructed so that they are immune to the various parasitic capacitances normally present in switched capacitor networks. One filter topology is capable of realizing any stable biquadratic z-domain transfer function, while the second one is only slightly less than fully general. Most commonly used transfer functions can be realized with either topology and will require only seven capacitors. The choice between the two topologies will generally be made on the basis of total capacitance required, dynamic range behavior, and sensitivity. A complete set of synthesis equations is given for both circuits which cover both the general and all the important special cases of the biquadratic transfer function. Finally, several examples are given which illustrate the synthesis procedures and the versatility of the filter topologies.

278 citations


01 Sep 1979
TL;DR: A theory of human-like reasoning in the general domain of designed physical systems, and in particular, electronic circuits, is presented, which can construct by qualitative causal analysis a mechanism graph describing the functional topology of the system.
Abstract: : This thesis presents a theory of human-like reasoning in the general domain of designed physical systems, and in particular, electronic circuits. One aspect of the theory, causal analysis, describes how the behavior of individual components can be combined to explain the behavior of composite systems. Another aspect of the theory, teleological analysis, describes how the notion that the system has a purpose can be used to aid this causal analysis. The theory is implemented as a computer program, which, given a circuit topology, can construct by qualitative causal analysis a mechanism graph describing the functional topology of the system. This functional topology is then parsed by a grammar for common circuit functions. Ambiguities are introduced into the analysis by the often several possible mechanisms which might describe the circuit's function. These are disambiguated by teleological analysis. The requirement that each component be assigned an appropriate purpose in the functional topology imposes a severe constraint which eliminates all of the ambiguities. Since both analyses are based on heuristics, the chosen mechanism is a rationalization of how the circuit functions, and does not guarantee that the circuit actually does function. This type of coarse understanding of circuits is useful for analysis, design and troubleshooting. (Author)

144 citations


Proceedings ArticleDOI
18 Jun 1979
TL;DR: A canonical switching cell is proposed from which the three basic DC-DC converter topologies can be derived and an optimum topology converter recently described by Cuk, et al., is shown to be a transformation of a basic topology.
Abstract: A canonical switching cell is proposed from which the three basic DC-DC converter topologies can be derived. In addition, it is possible to perform topological transformations which yield apparently new topologies. Upon examination, however, these topologies may prove to be identical to existing basic topologies. An optimum topology converter recently described by Cuk, et al.,is shown to be a transformation of a basic topology.

115 citations


Journal ArticleDOI
TL;DR: In this paper, a new approach to broadband matching which bypasses analytic gain-bandwidth theory and directly utilizes measured real frequency impedance data is applied to gain equalization and low-noise design of GaAs Shottky-barrier FET amplifiers.
Abstract: A new approach to broad-band matching which bypasses analytic gain-bandwidth theory and directly utilizes measured real frequency impedance data is applied to gain equalization and low-noise design of GaAs Shottky-barrier FET amplifiers. Neither the equalizer topology nor the analytic form of the system transfer function are initially assumed. These result from the design process. Examples include an octave-band FET amplifier design and a low-noise FET amplifier design. The equalizers are realized with lumped elements or transmission-fine sections. A single basic least squares program implements the design procedure.

108 citations


Proceedings ArticleDOI
01 Dec 1979
TL;DR: This paper is restricted to networks for geographically-localized parallel processing systems using 12 or more processors in a reconfigurable manner, as well as both fixed and dynamic word size systems.
Abstract: This is a survey of a variety of interconnection networks for reconfigurable parallel processing systems that have appeared in the literature. A system is reconfigurable if it may assume several architectural configurations, each of which is characterized by its own topology of activated interconnections between modules. 18 The systems whose networks will be examined include multiple-SIMD and MIMD systems, as well as both fixed and dynamic word size systems. This paper is restricted to networks for geographically-localized parallel processing systems using 12 or more processors in a reconfigurable manner. Related survey papers include References 1 , 3 , 10 , 19 , 20 , 45 - 47 .

76 citations


Journal ArticleDOI
01 Oct 1979
TL;DR: A new philosophically distinct technique called "parity simulation" produces a topologically isomorphic transformation of the system under study that exhibits a 1:1 correspondence, or parity, with the structure of the actual network.
Abstract: The time-varying topology created by the switch-mode operation of power semiconductor devices in energy conversion systems presents difficulties in analysis. Presently available methods for simulating the behavior of these systems include the use of the digital computer, the conventional analog computer, and the breadboard. A new philosophically distinct technique called "parity simulation" produces a topologically isomorphic transformation of the system under study; that is, it exhibits a 1:1 correspondence, or parity, with the structure of the actual network. A parity simulator utilizes terminal equivalent representations of network elements. The microcomputer based interface is highly user oriented. Nonlinear or time-varying element parameters are easily incorporated. Several simulation examples are presented.

72 citations


Proceedings ArticleDOI
18 Jun 1979
TL;DR: In this paper, a current-fed regulating converter using a new topology is described, which uses a novel switching scheme to increase the line voltage operating range, and is shewn to be one member of a family of circuits, each a little different from the others but sharing common characteristics.
Abstract: A current-fed regulating converter using a new topology is described. The circuit uses a novel switching scheme to increase the line voltage operating range. The converter circuit is shewn to be one member of a family of circuits, each a little different from the others but sharing common characteristics.

12 citations


Journal ArticleDOI
01 Feb 1979
TL;DR: In this paper, the design of elementary systems in which there are no multiple copies of files, transactions exhibit a high degree of geographic locality, and the network topology is a tree is discussed.
Abstract: Distributed systems range from the elementary to the very complex. This paper is concerned with the design of elementary systems in which there are no multiple copies of files, transactions exhibit a high degree of geographic locality, and the network topology is a tree. Issues considered include the selection of processors at different sites in the network, line topology and bandwidths, and allocation of application functions to processors. A case study is presented.

9 citations


Journal ArticleDOI
TL;DR: An optimal one-line diagram generator algorithm is presented and the problem is posed and solved as a longest path problem.
Abstract: An optimal one-line diagram generator algorithm is presented. The corresponding cctputer program drives the output device to draw a one-line diagram which is optimal in the sense that for a given drawing area, the minimum distance between elements of the diagram is a maximum. The computer program needs little additional information about the topology of the network to that normally supplied to a load flow program. The problem is posed and solved as a longest path problem. Examples of results of this program coupled to a load flow program are presented.

8 citations


Proceedings ArticleDOI
G. E. Bloom1, A. Eris1
18 Jun 1979
TL;DR: An experimental high frequency three output dc-dc converter design is presented in circuit detail, emphasizing the practical design needs of its contemporaty optimum topology ('CUK') output stages as discussed by the authors.
Abstract: An experimental high frequency three output dc-dc converter design is presented in circuit detail, emphasizing the practical design needs of its contemporaty optimum topology ('CUK) output stages. Power component selection criteria are also given along with suitable load protection methods against output voltage reversals at turn-on. Inductor coupling criteria for ripple current reductions at input/output ports are develop including an alternate method for external tuning inductance insertion. Results of corresponding empirical evaluations of a 200KHz, 55-W representative design are discussed.

7 citations


Journal ArticleDOI
L. Blahous1
01 Dec 1979
TL;DR: In this paper, it was shown that, in direct test circuits which yield undistinguishable prospective voltages, differences of 9.7% in the breaking capacity of an otherwise identical breaker are possible.
Abstract: The present IEC requirements for testing high-voltage circuit breakers impose certain conditions on the prospective voltage of the test circuit. This approach seems justified by the fact that the prospective voltage in theory describes exactly the test circuit in its elements and its topology. As in practice the prospective voltage is known only with certain tolerances, this method needs to assume that slight variations in the test circuit mean only slight variations in the circuit-breaker behaviour. By using the Urbanek equation to describe the circuit breaker, it is shown that, in direct test circuits which yield undistinguishable prospective voltages, differences of 9.7% in the breaking capacity of an otherwise identical breaker are possible. An explanation of this phenomenon is given and the limits are shown. In more realistic circuits, the result is verified in its trend.

Journal ArticleDOI
TL;DR: This paper presents a method for modelling the complex switching constraints and the operator logic of reasoning in a form adapted for automatic processing and discusses its advantages.

Proceedings Article
01 Jan 1979
TL;DR: In this paper, a canonical switching cell is proposed from which the three basic DC-DC converter topologies can be derived, and it is possible to perform topological transformations which yield apparently new topologies, however, these topologies may prove to be identical to existing basic topologies.
Abstract: A canonical switching cell is proposed from which the three basic DC-DC converter topologies can be derived In addition, it is possible to perform topological transformations which yield apparently new topologies Upon examination, however, these topologies may prove to be identical to existing basic topologies An optimum topology converter recently described by Cuk, et al,is shown to be a transformation of a basic topology

Proceedings ArticleDOI
18 Jun 1979
TL;DR: A new topology for a phase-controlled rectifier circuit with single and threephase circuits is presented and a mathematical analysis of the systems' parameters is developed.
Abstract: A new topology for a phase-controlled rectifier circuit is presented. Operation of this circuit is discussed in detail. Single and threephase circuits are shown. Experimental results are presented and a mathematical analysis of the systems' parameters is developed.

01 Jan 1979
TL;DR: A new topology for a phase-controlled recti­ fier circuit with single and threephase circuits is presented and a mathematical analysis of the systems' parameters is developed.
Abstract: A new topology for a phase-controlled recti­ fier circuit is presented. Operation of this circuit is discussed in detail. Single and threephase circuits are shown. Experimental results are presented and a mathematical analysis of the systems' parameters is developed.