Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

Basic mechanisms and modeling of single-event upset in digital microelectronics

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

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FinFETs and Other Multi-Gate Transistors

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

Radiation effects in SOI technologies

The production and propagation of single-event transients in scaled metal oxide semiconductor (CMOS) digital logic circuits are examined. Scaling trends to the 100-nm technology node are explored using three-dimensional mixed-level simulations, including both bulk CMOS and silicon-on-insulator (SOI) technologies. Significant transients in deep submicron circuits are predicted for particle strikes with linear energy transfer as low as 2 MeV-cm/sup 2//mg, and unattenuated propagation of such transients can occur in bulk CMOS circuits at the 100-nm technology node. Transients approaching 1 ns in duration are predicted in bulk CMOS circuits. Body-tied SOI circuits produce much shorter transients than their bulk counterparts, making them more amenable to transient filtering schemes based on temporal redundancy. Body-tied SOI circuits also maintain a significant advantage in single-event transient immunity with scaling.

Production and propagation of single-event transients in high-speed digital logic ICs

Advances in microelectronics performance and density continue to be fueled by the engine of Moore's law. Although lately this engine appears to be running out of steam, recent developments in advanced technologies have brought about a number of challenges and opportunities for their use in radiation environments. For example, while many advanced CMOS technologies have generally shown improving total dose tolerance, single-event effects continue to be a serious concern for highly scaled technologies. In this paper, we examine the impact of recent developments and the challenges they present to the radiation effects community. Topics covered include the impact of technology scaling on radiation response and technology challenges for both total dose and single-event effects. We include challenges for hardening and mitigation techniques at the nanometer scale. Recent developments leading to hardness assurance challenges are covered. Finally, we discuss future radiation effects challenges as the electronics industry looks beyond Moore's law to alternatives to traditional CMOS technologies.

Current and Future Challenges in Radiation Effects on CMOS Electronics

This paper investigates the transient response of 50-nm gate length fully and partially depleted SOI and bulk devices to pulsed laser and heavy ion microbeam irradiations. The measured transient signals on 50-nm fully depleted devices are very short, and the collected charge is small compared to older 0.25-/spl mu/m generation SOI and bulk devices. We analyze in detail the influence of the SOI architecture (fully or partially depleted) on the pulse duration and the amount of bipolar amplification. For bulk devices, the doping engineering is shown to have large effects on the duration of the transient signals and on the charge collection efficiency.

Direct measurement of transient pulses induced by laser and heavy ion irradiation in deca-nanometer devices

We use picosecond laser pulses to investigate single event upsets and related fundamental charge collection mechanisms in semiconductor microelectronic devices and circuits. By varying the laser wavelength the incident laser pulses deposit charge tracks of variable length, which form an approximation to the charge tracks resulting from high energy space particle strikes. We show how variation of the charge track length deposited by laser pulses allows the mechanisms of charge collection in semiconductor devices to be probed in a sensitive manner. With the aid of computer simulations, new insight into charge collection mechanisms for metal–semiconductor field effect transistor (MESFET) devices and heterojunction bipolar transistor devices is found. In the case of the MESFET we point out the correlation between charge collection in the device and the ensuing single event upset in the composite circuit. In favorable cases, we show how probing circuits with tunable laser pulses can estimate a charge collectio...

Pulsed laser-induced single event upset and charge collection measurements as a function of optical penetration depth

Exposing just the mechanical part (sensor) of MEMS accelerometers to protons and heavy ions caused large changes in outputs representing the measured acceleration for the ADXL50 and very small changes for the ADXL04. The large voltage shift measured for the ADXL50 is attributed to charge generated by the ions and trapped in dielectric layers below the moveable mass. The trapped charge alters the electric field distribution which, in turn, changes the output voltage. The construction of the ADXL04 differs from that of the ADXL50 in that the dielectric layers are covered with a conducting polycrystalline silicon layer that effectively screens out the trapped charge, leaving the output voltage unchanged.

The effects of radiation on MEMS accelerometers

A pulsed picosecond laser was used to measure the threshold for single event upset (SEU) and single event latchup (SEL) for a detailed study of a CMOS SRAM and a bipolar flip-flop. Comparing the ion and laser upset data for two such vastly different technologies gives a good measure of how versatile the technique is. The technique provided both consistent and repeatable results that agreed with published ion upset data for both types of circuits. However, measurements of the absolute threshold linear energy transfer (LET) using infrared laser light do not agree with those of the ions, being about 50% too high for the SRAMs, and about 20% too high for the bipolar flip-flops. The consistency of the results, together with the advantages of using a laser system, suggests that the pulsed laser can be used for SEU/SEL hardness assurance of integrated circuits. >

Pulsed laser-induced SEU in integrated circuits: a practical method for hardness assurance testing

The parasitic bipolar amplification in MOS/SOI transistors determines the SEU sensitivity of actual devices. This response is experimentally measured in a set of single transistors using a focused picosecond laser with submicrometer spatial resolution. This technique, validated by comparing the SEU behavior of registers irradiated with both laser and heavy ions, is relevant for both device physics and hardness assurance applications.

A.B. Campbell

Papers

Direct measurement of transient pulses induced by laser and heavy ion irradiation in deca-nanometer devices

Pulsed laser-induced single event upset and charge collection measurements as a function of optical penetration depth

The effects of radiation on MEMS accelerometers

Pulsed laser-induced SEU in integrated circuits: a practical method for hardness assurance testing

Laser probing of bipolar amplification in 0.25-/spl mu/m MOS/SOI transistors