A 0.9-V 60-muW delta-sigma modulator is designed using standard CMOS 0.13-mum technology. The modulator achieves 83-dB dynamic range in a signal bandwidth of 20 kHz with a sampling frequency of 2 MHz. The input-feedforward architecture is used to reduce the voltage swing of the integrators, which enables low-power amplifiers. By considering the characteristics of the modulator architecture, low-quiescent operational transconductance amplifiers are designed, which use positive feedback to increase dc gain. The designed modulator shows very high figure of merit among the state-of-the-art sub-l-V modulators.

/pdf/a-0-9-v-60-mu-hbox-w-1-bit-fourth-order-delta-sigma-3olakkdlrf.pdf

A 0.9-V 60- $\mu{\hbox {W}}$ 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range

This paper presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 $\mu \text{m}$ by 250 $\mu \text{m}$ . The proof-of-concept receiver was implemented in an STMicroelectronics’s 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a $4 \times 4$ subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor $\Delta \Sigma $ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator’s measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1-V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. The functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 mum CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

A digital feedforward sigma-delta modulator in an analog-to-digital converter and its modulation method are disclosed The modulator changes a feedforward path from an analog domain to a digital domain and processes it The modulator integrates an analog input by using a plurality of integrators, weights them, quantizes them by using a plurality of quantizers in a digital domain to output digital signals, and then adds up the thusly outputted digital signals by using a digital adder In case of a continuous time digital feedforward sigma-delta modulator (SDM), a digital signal outputted from the digital adder is weighted and then immediately inputted to the digital adder in the digital domain so as to be subtracted, allowing for digital feedforwarding Because the feedforward signal is processed in the digital domain, the area occupied by an analog circuit and power consumption can be reduced Also, because signals are added up in the digital domain, a digital output signal can be immediately used when an excess loop delay needs to be corrected Thus, because there is no need to convert the digital output signal into an analog signal by using a DAC, the DAC can be omitted

Digital feedforward sigma-delta modulator in analog-to-digital converter and modulation method thereof

This paper presents an overview of emerging circuits and systems techniques which are at the forefront of the state of the art in $\Delta\Sigma$ modulators, pushing their performance forward and giving rise to new generations of data converters. Among others, those strategies involving the development of new applications and paradigms—like RF/GHz-range $\Delta\Sigma$ digitisation, digital-assisted embedded loop filters, time-to-digital conversion and hybrid $\Delta\Sigma$ /Nyquist-rate architectures—are discussed, as well as the implications and design challenges derived from their integration in deep nanometer CMOS technologies. The envisioned $\Delta\Sigma$ techniques are presented in a systematic way around the main analog building blocks embedded in a $\Delta\Sigma$ modulator, i.e., the loop filter and the quantizer. Analysing the trends in the design of these blocks allows us to offer perspectives on how $\Delta\Sigma$ converters will evolve in the next years.

Next-Generation Delta-Sigma Converters: Trends and Perspectives

This brief addresses some practical issues on the implementation of the input-feedforward delta-sigma modulators. First, the timing constraint imposed by the input-feedforward path is identified and a possible method to relax the constraint is proposed. Second, the drawbacks of the analog adder needed before the quantizer are explained and a method to eliminate the adder is proposed

/pdf/on-the-implementation-of-input-feedforward-delta-sigma-1e4zhpcj08.pdf

On the implementation of input-feedforward delta-sigma modulators

We demonstrate a 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 mum CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 & dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0-3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).

/pdf/a-12-bit-3-125-mhz-bandwidth-0-3-mash-delta-sigma-modulator-12qbies7hj.pdf

A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator

A 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth is implemented in 0.18 mum CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0-3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).

/pdf/a-12-bit-3-125-mhz-bandwidth-0-3-mash-delta-sigma-modulator-4mckp1wtmj.pdf

A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator

http://ieeexplore.ieee.org/iel5/4/5109769/05109771.pdf

A 12-bit 3.125 MHz Bandwidth 0-3 MASH

In this brief, single-path time-interleaved delta-sigma modulators are analyzed and evaluated. It is found that finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the architecture. A hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators is proposed to mitigate the mismatch problem.

/pdf/combining-multipath-and-single-path-time-interleaved-delta-1fuwsn2nlh.pdf

A. Gharbiya

Papers

On the implementation of input-feedforward delta-sigma modulators

A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator

A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator

A 12-bit 3.125 MHz Bandwidth 0-3 MASH

Combining Multipath and Single-Path Time-Interleaved Delta-Sigma Modulators