A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-/spl mu/m CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V).

Low-power direct digital frequency synthesis for wireless communications

Oscillators are the subjects of intensive research. From Colpitts oscillators to phase locked loops, methods have been proposed to improve stability, frequency resolution, and spectral purity. Among the all-digital approaches, direct digital frequency synthesis are now available as integrated circuits and they output waveforms up to hundreds of megahertz. While DDS is slowly gaining acceptance in new system designs, methods used to improve the quality of the generated waveform are seldom used, even nowadays. The purpose of this article is to give an overview of the basics of DDS, along with simple formulas to compute bounds of the signal characteristics. Moreover, several methods, some patented, are presented to overcome some of the limits of the basic DDS with a focus on improving output signal quality.

Direct digital synthesis: a tool for periodic wave generation (part 1)

This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio A novel approach to evaluate, with reduced computational effort, the near optimal fixed-point coefficients which maximize the SFDR is described Several piecewise-linear and quadratic DDFS are implemented in the paper by using novel, single-summation-tree architectures The tradeoff between ROM and arithmetic circuits complexity is discussed, pointing out that a sensible silicon area reduction can be achieved by increasing ROM size and reducing arithmetic circuitry The use of fixed-width arithmetic can be combined with the single-summation-tree approach to further increase performances It is shown that piecewise-quadratic DDFSs become effective against piecewise-linear designs for an SFDR higher than 100 dBc Third-order DDFSs are expected to give advantages for an SFDR higher than 180 dBc The DDFS circuits proposed in this paper compare favorably with previously proposed approaches

High-performance direct digital frequency synthesizers using piecewise-polynomial approximation

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

Novel approach to the design of direct digital frequency synthesizers based on linear interpolation.

A new class of dynamic differential logic families, swing limited logic (SLL), is proposed for low-power high-performance applications. Two implementations of SLL, short-circuit current logic (SC/sup 2/L) and clock-pulse controlled logic (CPCL), are designed. Low power is achieved by aggressively reducing logic swing. Using a 0.35-/spl mu/m CMOS technology and a nominal supply voltage of 3.3 V, an SC/sup 2/L 8-bit carry ripple adder (CRA) is implemented. It offers an order of magnitude less energy-delay product than several other logic families. Furthermore, two multipliers are constructed to demonstrate how SLL can be used in large circuit applications.

Low-power high-performance arithmetic circuits and architectures

A novel low-power direct digital frequency synthesizer (DDFS) architecture is presented. The sine and cosine functions are generated by linearly interpolating between the sample points, reducing the size of the ROM look-up table to 416 bits for 9-bit output resolution. The DDFS is implemented in 0.8 /spl mu/m CMOS technology and features 60 dBc spectral purity, 48 Hz frequency resolution, with only 9.5 mW (@30 MHz, 3.3 V) power dissipation.

https://ieeexplore.ieee.org/iel5/6310/16877/00777351.pdf

A.M. Fahim

Papers

Low-power direct digital frequency synthesis for wireless communications

Low-power high-performance arithmetic circuits and architectures

A low-power direct digital frequency synthesizer architecture for wireless communications