Journal ArticleDOI
Low-power direct digital frequency synthesis for wireless communications
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TLDR
A low-power direct digital frequency synthesizer (DDFS) architecture is presented that uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware.Abstract:
A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-/spl mu/m CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V).read more
Citations
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Journal ArticleDOI
High-performance direct digital frequency synthesizers using piecewise-polynomial approximation
TL;DR: DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio.
Journal ArticleDOI
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter
TL;DR: An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented and considerably reduces power consumption by using several low- power techniques.
Journal Article
Novel approach to the design of direct digital frequency synthesizers based on linear interpolation.
TL;DR: It is shown that the complexity of synthesizers based on the new approach, in terms of the number of transistors and silicon area, is significantly less than that of previously presented DDFS designs of similar performance.
Journal ArticleDOI
Novel approach to the design of direct digital frequency synthesizers based on linear interpolation
TL;DR: In this article, the first quadrant of the sine function is approximated with a number of linear segments, and a detailed and systematic procedure for the selection of linear segment coefficients achieving a desired spurious free dynamic range (SFDR) is proposed.
Journal ArticleDOI
Phase to sinusoid amplitude conversion techniques for direct digital frequency synthesis
TL;DR: The authors present a review of phase to sine amplitude conversion (PSAC) techniques for direct digital frequency synthesis (DDFS) following a systematic classification of techniques, namely angular decomposition, angular rotation, sining amplitude compression, polynomial approximation, and analogue approaches.
References
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Journal ArticleDOI
A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance
H.T. Nicholas,Henry Samueli +1 more
TL;DR: A monolithic CMOS direct digital frequency synthesizer (DDFS) is presented which simultaneously achieves high spectral purity and wide bandwidth and an efficient look-up table method for calculating the sine function reduces ROM storage requirements by a factor of 128:1.
Proceedings ArticleDOI
The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects
TL;DR: Techniques for the design of VLSI architectures for direct digital frequency synthesis have been introduced that allow for the optimization of the spurious response in the presence of finite-wordlength effects and these techniques have been applied to design a 14-bit-output DDFS.
Journal ArticleDOI
CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications
TL;DR: Using a 3.5-/spl mu/m gate length complementary metal-oxide-semiconductor/silicon-on-sapphire technology, a single-chip, radiation-hardened, direct digital frequency synthesizer has been developed.
Journal ArticleDOI
A 200 MHz quadrature digital synthesizer/mixer in 0.8 /spl mu/m CMOS
Loke Kun Tan,Henry Samueli +1 more
TL;DR: A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented in this article with a spectral purity of -84.3 dBc and frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles.
Journal ArticleDOI
Supply voltage scaling for temperature insensitive CMOS circuit operation
TL;DR: In this paper, the authors investigated the optimum supply voltage which results in temperature insensitive operation is proportional to the threshold voltage, which enables a single battery cell operation with 0.35- and 0.25-/spl mu/m size features.