A physical understanding of both intrinsic and extrinsic noise mechanisms in a MOSFET is developed. Intrinsic noise mechanisms fundamental to device operation include channel thermal noise, induced gate noise, and induced substrate noise. While the effect of channel thermal noise is observable at zero drain-to-source voltage, the induced gate and substrate noise do not manifest themselves under these conditions. However, the attendant fluctuations in the channel charge are observable by the passage of electric current through the device. Extrinsic noise mechanisms manifested due to structural evolution of the MOSFET include the distributed gate resistance noise, distributed substrate resistance noise, bulk charge effects, substrate current supershot noise, gate current noise, excess channel noise, and 1/f noise. Where available, compact noise models covering these noise mechanisms are explained. Also, where possible, methods of suppression of these mechanisms are highlighted. A survey of current public domain MOS models is presented, and a lack of comprehensive coverage of noise models is noted. Open areas of MOSFET noise research in the sub-hundred-nanometer regime are also highlighted. With suitable adaptation, noise concepts elucidated in the context of MOS transistors have a much wider applicability to the operation of HEMTs, JFETs, MESFETs, and other field-effect devices

Compact Noise Models for MOSFETs

This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio A novel approach to evaluate, with reduced computational effort, the near optimal fixed-point coefficients which maximize the SFDR is described Several piecewise-linear and quadratic DDFS are implemented in the paper by using novel, single-summation-tree architectures The tradeoff between ROM and arithmetic circuits complexity is discussed, pointing out that a sensible silicon area reduction can be achieved by increasing ROM size and reducing arithmetic circuitry The use of fixed-width arithmetic can be combined with the single-summation-tree approach to further increase performances It is shown that piecewise-quadratic DDFSs become effective against piecewise-linear designs for an SFDR higher than 100 dBc Third-order DDFSs are expected to give advantages for an SFDR higher than 180 dBc The DDFS circuits proposed in this paper compare favorably with previously proposed approaches

High-performance direct digital frequency synthesizers using piecewise-polynomial approximation

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

Novel approach to the design of direct digital frequency synthesizers based on linear interpolation.

This paper presents a novel approach to the design of direct digital frequency synthesizers (DDFSs) with phase-to-sinusoid amplitude conversion blocks based on linear interpolation. For such DDFSs, the first quadrant of the sine function is approximated with a number of linear segments. Simple control circuitry reconstructs a full sine wave by symmetry. DDFS architectures using linear interpolation are first discussed, and an analysis of their spectral properties is given. From this analysis, an upper bound is provided for the spurious free dynamic range (SFDR) that can be attained for a given number of linear segments. A detailed and systematic procedure for the selection of linear segment coefficients achieving a desired SFDR is then proposed. A generalized multiplierless linear interpolation DDFS architecture is described, and specific designs achieving 84 and 96 dBc of SFDR are discussed and compared with previous work. It is shown that the complexity of synthesizers based on the new approach, in terms of the number of transistors and silicon area, is significantly less than that of previously presented DDFS designs of similar performance.

Novel approach to the design of direct digital frequency synthesizers based on linear interpolation

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-/spl mu/m CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V).

Low-power direct digital frequency synthesis for wireless communications

A direct digital frequency synthesizer for generating a digital sine or cosine function waveform receive digital input. Memory stores digital samples along portions of sine and cosine function waveforms. The memory outputs the digital samples in response to a first portion of the digital input. Control logic is responsive to the digital input and controls the output of the digital samples from the memory to allow digital samples along a complete cycle of the sine or cosine function waveform to be output even though only portions of the sine and cosine function waveforms are stored in the memory. A linear interpolator receives a second portion of the digital input and modifies digital samples output by the memory to generate intermediate digital samples between the digital samples stored in the memory to improve accuracy.

Low-power direct digital frequency synthesizer architecture

A novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit technique; simple buffers, logic gates, and master-slave latches. Their performance, regarding speed, area, and power, was compared to that of CMOS for different technologies and supply voltages. Both device and circuit simulations were used. A design procedure for the feedback circuit and the effects of scaling on that procedure were studied and reported. >

Novel low-voltage low-power full-swing BiCMOS circuits

A new software tool TRASIM (Two-Dimensional Transient Simulator) has been developed for arbitrary, planar semiconductor devices. A finite difference technique is employed with a modified, decoupled Gummel-like method. The memory requirements are reduced significantly compared to the conventionally used Newton-like methods. TRASIM exhibits a good stability and convergence rate, and user interaction with the computational process is significantly reduced. Low memory requirements and efficiency make the method attractive for the future 3-D applications. The software uses the drift-diffusion model, with up-to-date mobility and lifetime models. External RC-chains may be connected to device electrodes. Numerical examples are presented illustrating the advantages of the modified Gummel method over the Newton method, for transient simulation. >

TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices

We present results of a two-demensional (2D) numerical simulation of high-frequency noise in a short-channel metal-oxide-semiconductor field-effect transistors (MOSFET). Conventionally this noise in MOSFETs is treated as a thermal noise with a rather slow temperature dependence of the noise spectra. On contrary, the results obtained indicate that this dependence is more of an exponential kind, typical for a shot noise. Shot noise is conventionally related to a forward biased p-n junction where the current is mostly due to diffusion in the quasi-neutral region. We therefore speculate that most likely in short channel MOSFETs most of the high-frequency noise is produced not in the cut-off region of the channel but near the source side of the channel where diffusion current component is dominant.

https://iopscience.iop.org/article/10.1143/JJAP.39.1690/pdf

M.S. Obrecht

Papers

Low-power direct digital frequency synthesis for wireless communications

Low-power direct digital frequency synthesizer architecture

Novel low-voltage low-power full-swing BiCMOS circuits

TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices

Simulation of Temperature Dependence of Microwave Noise in Metal-Oxide-Semiconductor Field-Effect Transistors