This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.


Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly 
Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence 
Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products 
Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes



Table of Contents


Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:?Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.

Electronic Design Automation: Synthesis, Verification, and Test

. Compositional testing concerns the testing of systems that consist of communicating components which can also be tested in isolation. Examples are component based testing and interoperability testing. We show that, with certain restrictions, the ioco-test theory for conformance testing is suitable for compositional testing, in the sense that the integration of fully conformant components is guaranteed to be correct. As a consequence, there is no need to re-test the integrated system for conformance.

This result is also relevant for testing in context, since it implies that every failure of a system embedded in a test context can be reduced to a fault of the system itself.

/pdf/compositional-testing-with-ioco-t1agfggkth.pdf

Compositional Testing with ioco

This paper addresses the problem of test generation from partially specified deterministic finite state machines (FSMs) that may have indistinguishable states and, thus, are not necessarily reduced (minimized). The known methods for checking experiments that are based on state identification are not applicable to unreduced machines. We propose the so-called state-counting approach that is directly applicable to unreduced FSMs. The approach generalizes the idea of state identification in test generation methods for deterministic machines.

Testing from partial deterministic FSM specifications

The annotated bibliography highlights work in the area of algorithmic test generation from formal specifications with guaranteed fault coverage, i.e., fault model-driven test derivation. A fault model is understood as a triple, comprising a finite state specification, conformance relation and fault domain that is the set of possible implementations. The fault model can be specialized to Input/Output FSM, Labeled Transition System, or Input/Output Automaton and to a number of conformance relations such as FSM equivalence, reduction or quasiequivalence, trace inclusion or trace equivalence and others. The fault domain usually reflects test assumptions, as an example, it can be the universe of all possible I/O FSMs with a given number of states, a classical fault domain in FSM-based testing. A test suite is complete with respect to a given fault model when each implementation from the fault domain passes it if and only if the postulated conformance relation holds between the implementation and its specification. A complete test suite is said to provide fault coverage guarantee for a given fault model.

Fault Model-Driven Test Derivation from Finite State Models: Annotated Bibliography

In this paper, conformance testing of protocols specified as nondeterministic finite state machines is considered. Protocol implementations are assumed to be deterministic. In this testing scenario, the conformance relation becomes a preorder, so-called reduction relation between FSMs. The reduction relation requires that an implementation machine produces a (sub)set of output sequences that can be produced by its specification machine in response to every input sequence. A method for deriving tests with respect to the reduction relation with full fault coverage for deterministic implementations is proposed based on certain properties of the product of specification and implementation machines.

/pdf/testing-deterministic-implementations-from-nondeterministic-5e79ad26ll.pdf

Testing deterministic implementations from nondeterministic FSM specifications

The problem of designing a component that, combined with a known part of a system, conforms to a given overall specification arises in several applications ranging from logic synthesis to the design of discrete controllers. We cast the problem as solving abstract equations over languages. Language equations can be defined with respect to several language composition operators such as synchronous composition, /spl middot/, and parallel composition, /spl square/; conformity can be checked by language containment. In this paper, we address parallel language equations. Parallel composition arises in the context of modeling delay-insensitive processes and their environments. The parallel composition operator models an exchange protocol by which an input is followed by an output after a finite exchange of internal signals. It abstracts a system with two components with a single message in transit, such that at each instance either the components exchange messages or one of them communicates with its environment, which submits the next external input to the system only after the system has produced an external output in response to the previous input. We study the most general solutions of the language equation A/spl square/X/spl sube/C, and define the language operators needed to express them. Then we specialize such equations to languages associated with important classes of automata used for modeling systems, e.g., regular languages and FSM languages. In particular, for A/spl square/X/spl sube/C, we give algorithms for computing: the largest FSM language solution, the largest complete solution, and the largest solution whose composition with A yields a complete FSM language. We solve also FSM equations under bounded parallel composition. In this paper, we give concrete algorithms for computing such solutions, and state and prove their correctness.

/pdf/solution-of-parallel-language-equations-for-logic-synthesis-6js2zd4t3d.pdf

Solution of parallel language equations for logic synthesis

The paper addresses grey-box testing of a system of communicating finite state machines under the assumptions that the system’s structure is preserved in all potential implementations, and that at most one component can be faulty. Several possible testing strategies which rely on these assumptions in various manners are presented and compared. The ideas behind these strategies are explained on a simple serial composition of two communicating FSMs. The existing FSM-based test derivation methods are assessed for their applicability to solve the problems arising from grey-box testing.

/pdf/testing-strategies-for-communicating-fsms-2s6vuorls8.pdf

Testing strategies for communicating FSMs

We address in this paper the problem of detecting faults located in a given component embedded within a composite system. The system is represented as two communicating FSMs, a component FSM inaccessible for testing and a context machine that models the remaining part of the system which is assumed to be correctly implemented. We elaborate a systematic approach for deriving external tests which can detect all predefined types of faults in the embedded component. The approach. is based on the construction a proper characterization of the conforming behavior of the component in context, derivation of internal tests and translation into external tests.

/pdf/fault-detection-in-embedded-components-5cw0wuta70.pdf

Fault detection in embedded components

The paper addresses the problem of designing a component that combined with a known part of a system, called the context FSM, is a reduction of a given specification FSM. We study compositionally progressive solutions of synchronous FSM equations. Such solutions, when combined with the context, do not block any input that may occur in the specification, so they are of practical use. We show that, if a synchronous FSM equation has a compositionally progressive solution, then there is a largest regular compositionally progressive solution including all of them. We provide two different algorithms to compute a largest regular compositionally progressive solution: one deletes all compositionally non-progressive strings from a largest solution, the other splits states of a largest solution and then removes those inducing a non-progressive composition.

Compositionally Progressive Solutions of Synchronous FSM Equations

Design For Testability (DFT) is understood as the process of introducing some features into a communication software that facilitate the testing process of protocol implementations. DFT at the implementation level deals with a particular realization on a given platform, whereas DFT at the specification level affects all possible implementations regardless of the implementation process. In this paper, we propose in the first part, a generic framework of design for testability where DFT activity is integrated in the communication software development process. A generic model for testability transformation based on modification of a given specification and testability measurement is explained. In the second part, we address one particular problem of DFT, the problem of analyzing the testability of a given module specified as a finite state machine. Transformations in this paper are not the main objective, but they are used to illustrate how testability can be enhanced by finding an augmentation of the given protocol behavior such that a newly obtained specification is more testable than the original one A measure of testability of a protocol entity is assumed to be based on the shortest length of a test suite needed to achieve guaranteed coverage of certain faults. We consider the FSM model of a protocol machine and propose a classification method based on the formalized notions of controllability and observability.

https://link.springer.com/content/pdf/10.1007%2F978-0-387-34988-6_15.pdf

A. Petrenko

Papers

Solution of parallel language equations for logic synthesis

Testing strategies for communicating FSMs

Fault detection in embedded components

Compositionally Progressive Solutions of Synchronous FSM Equations

Towards testable communication software