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A.T.A. Zegers-van Duijnhoven
Researcher at Philips
Publications - 15
Citations - 902
A.T.A. Zegers-van Duijnhoven is an academic researcher from Philips. The author has contributed to research in topics: Noise (electronics) & Flicker noise. The author has an hindex of 9, co-authored 14 publications receiving 866 citations.
Papers
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Journal ArticleDOI
Noise modeling for RF CMOS circuit simulation
A.J. Scholten,L.F. Tiemeijer,R. van Langevelde,R.J. Havens,A.T.A. Zegers-van Duijnhoven,V. C. Venezia +5 more
TL;DR: In this paper, a nonquasi-static channel segmentation model was proposed to predict both drain and gate current noise in 0.18-/spl mu/m CMOS technology.
Journal ArticleDOI
RF-CMOS performance trends
Pierre H. Woerlee,M.J. Knitel,R. van Langevelde,D.B.M. Klaassen,L.F. Tiemeijer,A.J. Scholten,A.T.A. Zegers-van Duijnhoven +6 more
TL;DR: In this paper, the impact of scaling on the analog performance of MOS devices at RF frequencies was studied and a scaling methodology for RF-CMOS based on limited linearity degradation was proposed.
Proceedings ArticleDOI
CMOS device optimization for mixed-signal technologies
Peter Stolk,Hans Tuinhout,Ray Duffy,E. Augendre,L.P. Bellefroid,M.J.B. Bolt,Jeroen Croon,C.J.J. Dachs,F.R.J. Huisman,A.J. Moonen,Youri Victorovitch Ponomarev,R.F.M. Roes,M. Da Rold,E. Seevinck,K.N. Sreerambhatla,R. Surdeanu,R.M.D.A. Velghe,M. Vertregt,M.N. Webster,N.K.J. van Winkelhoff,A.T.A. Zegers-van Duijnhoven +20 more
TL;DR: This paper studies the suitability of CMOS device technology for mixed-signal applications to propose new device solutions such as metal gate integration and asymmetric (source-side-only) workfunction modification.
Proceedings ArticleDOI
Impact of process scaling on 1/f noise in advanced CMOS technologies
TL;DR: In this paper, the influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Sv/sub gate/ has been experimentally investigated.
Proceedings ArticleDOI
Compact modeling of drain and gate current noise for RF CMOS
A.J. Scholten,L.F. Tiemeijer,R. van Langevelde,R.J. Havens,V. C. Venezia,A.T.A. Zegers-van Duijnhoven,B. Neinhus,Christoph Jungemann,D.B.M. Klaasen +8 more
TL;DR: In this article, a model for RF CMOS circuit design is presented that is capable of predicting drain and gate current noise without adjusting any parameters, and the presence of noise associated with avalanche multiplication and shot noise of the direct-tunneling gate current in leaky dielectrics is revealed.