Showing papers by "Aarno Parssinen published in 2003"

Bluetooth rf based rf-tag read/write station

Abstract: Radio device having a radio receiver, a radio transmitter and a signal processor (62), wherein the radio receiver is responsive to an incoming analog radio signal (72) for providing a down converted and modulated signal to signal processor (62), wherein the radio transmitter is responsive is responsive to an output signal from signal processor (62) for transmission as an outgoing analog radio signal (70), characterized by control logic (66) for controlling the radio device in two modes, a first mode for operating as a bluetooth device and a second mode for operating as an RF tag reader.

A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

Abstract: A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.

Method and apparatus providing calibration technique for RF performance tuning

Abstract: A method is disclosed for operating a RF receiver of a communications equipment, as is circuitry for implementing the method. The method includes, while operating under the control of a data processor of the communications equipment, generating a calibration signal; injecting the calibration signal into a low noise amplifier (LNA) of the RF receiver; measuring a downconverted response of the receiver at a plurality of different frequencies of the calibration signal, or measuring the downconverted response of the receiver at a plurality of different LNA tuning combinations using a fixed calibration frequency, and at least one of tuning a resonance frequency of at least one LNA resonator based on the measured downconverted response so as to compensate at least for variations in component values that comprise the at least one resonator, or adjusting the linearity of the receiver. In one embodiment the calibration signal is generated using one of a noise source located upstream from the LNA and a transmitter signal, having an AM component, that leaks into the receiver through a duplex filter.

A 3-V 230-MHz CMOS Decimation Subsampler

Abstract: The use of subsampling for frequency downconversion and related tradeoffs in radio receivers are discussed. It is found that using the highest possible sampling frequency both relaxes anti-alias filtering requirements and reduces the effect of clock jitter. However, high-speed switched-capacitor circuits are difficult to design and they are typically power consuming. A switched-capacitor decimation sampler is proposed as a way to achieve more optimal sampling frequencies both at the input and the output of the sampler. The design and experimental results of a 3-V 230-MHz CMOS decimation subsampler are presented. The sampler achieves an input referred noise density of 44 nV//spl radic/Hz, an IIP/sub 3/ of +19.5 dBV, and a -52-dBc worst mixing product from clock skew with a 200-MHz input.

Analysis of packaging effects and optimization in inductively degenerated common-emitter low-noise amplifiers

Abstract: The effects of packaging on the performance of inductively degenerated common-emitter low-noise amplifiers (LNAs) are examined and the equations describing the input impedance, transconductance, voltage gain, and noise figure of the packaged amplifier are derived. From the equations, several guidelines for the LNA design are obtained and a systematic approach for the LNA design can be derived. Furthermore, by applying the formulas, the performance of the amplifier can be readily estimated and optimized in the very early stage of the circuit design, immediately as the process data is available. The measurement results of the implemented 0.35-/spl mu/m SiGe RF front-end with an inductively degenerated common-emitter LNA at 1.575 GHz agree well with calculations and simulations.

Voltage controlled capacitive elements having a biasing network

Abstract: A voltage-controlled oscillator includes a resonator circuit and a voltage source. The resonator circuit includes a capacitive circuit that has a plurality of analog voltage controlled capacitive elements coupled to one another. The voltage source is coupled to the resonator circuit and provides a voltage to the plurality of analog voltage controlled capacitive elements. Each of the plurality of analog voltage controlled capacitive elements is activated as a function of the voltage thereby increasing linearity of a frequency tuning voltage parameter of the resonator.

System and method for tuning an oscillator

Abstract: A voltage-controlled oscillator includes a resonator circuit and a voltage source. The resonator circuit includes a capacitive circuit that has a plurality of analog voltage controlled capacitive elements coupled to one another. The voltage source is coupled to the resonator circuit and provides a voltage to the plurality of analog voltage controlled capacitive elements. Each of the plurality of analog voltage controlled capacitive elements is activated as a function of the voltage thereby increasing linearity of a frequency tuning voltage parameter of the resonator.

A 3-V 230-MHz CMOS decimation subsampler

Abstract: The use of subsampling for frequency downconversion and related tradeoffs in radio receivers are discussed. It is found that using the highest possible sampling frequency both relaxes anti-alias filtering requirements and reduces the effect of clock jitter. However, high-speed switched-capacitor circuits are difficult to design and they are typically power consuming. A switched-capacitor decimation sampler is proposed as a way to achieve more optimal sampling frequencies both at the input and the output of the sampler. The design and experimental results of a 3-V 230-MHz CMOS decimation subsampler are presented. The sampler achieves an input referred noise density of 44 nV//spl radic/Hz, an IIP/sub 3/ of +19.5 dBV, and a -52-dBc worst mixing product from clock skew with a 200-MHz input.

A 3-V 230-MHz CMOS decimation subsampler.

Abstract: The use of subsampling for frequency downconversion and related tradeoffs in radio receivers are discussed. It is found that using the highest possible sampling frequency both relaxes anti-alias filtering requirements and reduces the effect of clock jitter. However, high-speed switched-capacitor circuits are difficult to design and they are typically power consuming. A switched-capacitor decimation sampler is proposed as a way to achieve more optimal sampling frequencies both at the input and the output of the sampler. The design and experimental results of a 3-V 230-MHz CMOS decimation subsampler are presented. The sampler achieves an input referred noise density of 44 nV//spl radic/Hz, an IIP/sub 3/ of +19.5 dBV, and a -52-dBc worst mixing product from clock skew with a 200-MHz input.

Direct conversion receiver for GSM900, DCS1800, PCS1900, and WCDMA

Abstract: A single-chip, multi-mode direct conversion receiver designed for GSM900, DCS 1800, PCS 1900, and UTRA/FDD WCDMA, applications is described. The low-noise amplifier uses only four on-chip inductors. The downconversion mixers include a method to improve the receiver IIP2 to over +40dBm. The baseband circuit achieves over +90dBV IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8dB in all GSM modes, and 3.5dB in WCDMA. The power consumption in all GSM modes is 42mW and in WCDMA 50mW. The silicon area is 10mm/sup 2/.