A method for applying the application of reading multiple NFC tags. By examining the context of the reading, the identification of the NFC tags, and a direction, pattern and/or sequence of reading, a corresponding action is determined and requested.

Combination process interaction

Commissioning a lighting system is disclosed. A user can be provided with a pointing device capable of emitting or returning a signal which can be received by detectors co-located with each fixture in the lighting system. The user can add a fixture to a group by aiming the pointing device at the fixture when the fixture is not assigned to the group, and the user can remove a fixture from a group in the same way when the fixture was previously assigned to the group. Additional user gestures are also disclosed.

Commissioning lighting systems

Recent studies from several hyperscalars pinpoint to embedding layers as the most memory-intensive deep learning (DL) algorithm being deployed in today's datacenters. This paper addresses the memory capacity and bandwidth challenges of embedding layers and the associated tensor operations. We present our vertically integrated hardware/software co-design, which includes a custom DIMM module enhanced with near-memory processing cores tailored for DL tensor operations. These custom DIMMs are populated inside a GPU-centric system interconnect as a remote memory pool, allowing GPUs to utilize for scalable memory bandwidth and capacity expansion. A prototype implementation of our proposal on real DL systems shows an average 6.2-17.6× performance improvement on state-of-the-art DNN-based recommender systems.

TensorDIMM: A Practical Near-Memory Processing Architecture for Embeddings and Tensor Operations in Deep Learning

Many modern and emerging applications must process increasingly large volumes of data. Unfortunately, prevalent computing paradigms are not designed to efficiently handle such large-scale data: The energy and performance costs to move this data between the memory subsystem and the CPU now dominate the total costs of computation. This forces system architects and designers to fundamentally rethink how to design computers. Processing-in-memory (PIM) is a computing paradigm that avoids most data movement costs by bringing computation to the data. New opportunities in modern memory systems are enabling architectures that can perform varying degrees of processing inside the memory subsystem. However, many practical system-level issues must be tackled to construct PIM architectures, including enabling workloads and programmers to easily take advantage of PIM. This article examines three key domains of work toward the practical construction and widespread adoption of PIM architectures. First, we describe our work on systematically identifying opportunities for PIM in real applications and quantify potential gains for popular emerging applications (e.g., machine learning, data analytics, genome analysis). Second, we aim to solve several key issues in programming these applications for PIM architectures. Third, we describe challenges that remain for the widespread adoption of PIM.

Processing-in-memory: A workload-driven perspective

In the current information age, the realization of memory devices with energy efficient design, high storage density, nonvolatility, fast access, and low cost is still a great challenge. As a promising technology to meet these stringent requirements, nonvolatile multistates memory (NMSM) has attracted lots of attention over the past years. Owing to the capability to store data in more than a single bit (0 or 1), the storage density is dramatically enhanced without scaling down the memory cell, making memory devices more efficient and less expensive. Multistates in a single cell also provide an unconventional in-memory computing platform beyond the Von Neumann architecture and enable neuromorphic computing with low power consumption. In this review, an in-depth perspective is presented on the recent progress and challenges on the device architectures, material innovation, working mechanisms of various types of NMSMs, including flash, magnetic random-access memory (MRAM), resistive random-access memory (RRAM), ferroelectric random-access memory (FeRAM), and phase-change memory (PCM). The intriguing properties and performance of these NMSMs, which are the key to realizing highly integrated memory hierarchy, are discussed and compared.

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Nonvolatile Multistates Memories for High-Density Data Storage.

The physical memory capacity of servers is expected to increase drastically with the deployment of the forthcoming non-volatile memory technologies. This is a welcomed improvement for the emerging data-intensive applications. For such servers to be cost-effective, nonetheless, we must cost-effectively increase compute throughput and memory bandwidth commensurate with the increase in memory capacity without compromising the application readiness. Tackling this challenge, we present Memory Channel Network (MCN) architecture in this paper. Specifically, first, we propose an MCN DIMM, an extension of a buffered DIMM where a small but capable processor called MCN processor is integrated with a buffer device on the DIMM for near-memory processing. Second, we implement device drivers to give the host and MCN processors in a server an illusion that they are independent heterogeneous nodes connected through an Ethernet link. These allow the host and MCN processors in a server to run a given data-intensive application together based on popular distributed computing frameworks such as MPI and Spark without any change in the host processor hardware and its application software, while offering the benefits of high-bandwidth and low-latency communication between the host and MCN processors over the memory channels. As such, MCN can serve as an application-transparent framework which can seamlessly unify the near-memory processing within a server and the distributed computing across such servers for data-intensive applications. Our simulation running the full software stack shows that a server with 8 MCN DIMMs offers 4.56 x higher throughput and consume 47.5% less energy than a cluster with 9 conventional nodes connected through Ethernet links, as it facilitates up to 8.17 x higher aggregate DRAM bandwidth utilization. Lastly, we demonstrate the feasibility of MCN with an IBM POWER8 system and an experimental buffered DIMM.

Application-transparent near-memory processing architecture with memory channel network

Disclosed are embodiments of a radio frequency identification (RFID) authentication system and an associated authentication methodology The embodiments incorporate an identification device (eg, an identification badge, a key fob, etc) with an embedded RFID tag The embedded RFID tag is associated with a specific user and stores a private key generated as part of a public key-private key encryption scheme The private key is read by an RFID reader and used to decode public key encrypted data stored within or accessible by a computer system (eg, a desktop computer system, a laptop computer system, a personal digital assistant (PDA), a digital fax machine, wireless telephone, etc) Thus, the embodiments provide a portable way to use public key-private key encryption scheme data anywhere using RFID technology

Radio frequency identification (RFID) based authentication system and methodology

Disclosed is a self-contained hardware-based authentication system that incorporates different authentication protocols for access to soft and/or hard assets with different security levels. The system embodiments include the use of a RFID device that comprises dual RFID tags operating under different frequencies. Specifically, one RFID tag operates on a public frequency and, when activated, transmits an identifier encrypted using a public key. The other RFID tag operates on a private frequency and, when activated, transmits a private key that can be used to decrypt the encrypted identifier. Upon receipt by a processor (e.g., a local processor or security server) of a request for access to a specific asset, a security level for the specific asset is determined. Then, depending upon the particular security level (e.g. low, medium or high) different authentication protocols are instituted using the RFID device. Also disclosed are embodiments of an associated authentication methodology.

Radio frequency identification (rfid) based authentication methodology using standard and private frequency rfid tags

We demonstrate the use of an FPGA as a memory buffer in a POWER8® system, creating a novel prototyping platform that enables innovation in the memory subsystem of POWER-based servers. Our platform, called ConTutto, is pin-compatible with POWER8 buffered memory DIMMs and plugs into a memory slot of a standard POWER8 processor system, running at aggregate memory channel speeds of 35 GB/s per link. ConTutto, which means “with everything”, is a platform to experiment with different memory technologies, such as STT-MRAM and NAND Flash, in an end-to-end system context. Enablement of STTMRAM and NVDIMM using ConTutto shows up to 12.5x lower latency and 7.5x higher bandwidth compared to the respective technologies when attached to the PCIe bus. Moreover, due to the unique attach-point of the FPGA between the processor and system memory, ConTutto provides a means for in-line acceleration of certain computations on-route to memory, and enables sensitivity analysis for memory latency while running real applications. To the best of our knowledge, ConTutto is the first ever FPGA platform on the memory bus of a server class processor. CCS CONCEPTS •Hardware → Emerging technologies → Analysis and design of emerging devices and systems; • Computer systems organization → Architectures → Other architectures → Reconfigurable computing;

Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor

Artificial intelligence (AI), specifically Deep Learning (DL) techniques are used for real-time analytics, fraud detection, autonomous driving, and speech recognition etc. These power and data hungry DL applications on cloud and at edge has increased Deep Neural Network (DNN) complexity. Multi-tiered Compute, Memory and Storage arrangements can help push AI applications by providing faster access to high volume of data and optimizing cost. AI memory needs are quite different from traditional workloads, requiring faster access to data. DRAM manufacturers struggle with challenges like density growth, cost and bit errors. High Bandwidth Memory (HBM) and GDDR help achieve almost real time access to the memory. Each of these memories have range of system trade-offs such as density, power efficiency and bandwidth. Unlike traditional memory, Persistent memory like MRAM, Phase change memory (PCM), Resistive RAM (ReRAM), Carbon Nanotube RAM (NRAM) etc. provide non-volatility. Persistent memory has a potential to reduce the latency and cost gap between DRAM and Storage. Persistent Memory is a promising technology for driving AI but face challenges of cost, scaling and reliability. Bigger the training data set, better the inference drawn by DNN. This comes with a huge storage demand. With increase in layer count of 3D NAND and innovations in circuit design and process technology, flash enables multi-bit TLC and QLC densities. PCIe bus with SSD provides low latency and high throughput, making flash the most optimal solution for AI storage. High aspect ratio channel etch, staircase contacts, defect control etc. are some of the challenges with upcoming flash generations.

Adam J. McPadden

Papers

Application-transparent near-memory processing architecture with memory channel network

Radio frequency identification (RFID) based authentication system and methodology

Radio frequency identification (rfid) based authentication methodology using standard and private frequency rfid tags

Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor

Memory Technology enabling the next Artificial Intelligence revolution