Kyu-hyoun Kim

TL;DR: An analysis of DDR4 DRAM's FGR feature is conducted, and there is no one-size-fits-all option across a variety of applications, and Adaptive Refresh is presented, a simple yet effective mechanism that dynamically chooses the best FGR mode for each application and phase within the application.

TL;DR: In this paper, an advanced memory has been proposed that includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error controller coding circuitry detecting an error in the received commands.

TL;DR: In this article, a 4-core AI chip in 7nm EUV technology is presented to exploit cutting-edge algorithmic advances for iso-accurate models in low-precision training and inference to achieve leading-edge power-performance.

TL;DR: In this article, a memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver is used to generate a delayed clock having a time relation to the received clock as determined by the delay instruction bits.

TL;DR: In this paper, the authors describe a DRAM subsystem, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM.