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Adrian Cristal
Researcher at Barcelona Supercomputing Center
Publications - 176
Citations - 3188
Adrian Cristal is an academic researcher from Barcelona Supercomputing Center. The author has contributed to research in topics: Transactional memory & Shared memory. The author has an hindex of 27, co-authored 172 publications receiving 2951 citations. Previous affiliations of Adrian Cristal include Polytechnic University of Catalonia & Microsoft.
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Proceedings ArticleDOI
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime
TL;DR: New techniques that can tolerate high bit error rates without requiring prohibitively strong ECC are developed, called Flash Correct-and-Refresh (FCR), which provide 46× average lifetime improvement on a variety of workloads at no additional hardware cost.
Proceedings ArticleDOI
Redundant memory mappings for fast access to large memories
Vasileios Karakostas,Jayneel Gandhi,Furkan Ayar,Adrian Cristal,Mark D. Hill,Kathryn S. McKinley,Mario Nemirovsky,Michael M. Swift,Osman Unsal +8 more
TL;DR: Redundant Memory Mappings (RMM) is proposed, which leverage ranges of pages and provides an efficient, alternative representation of many virtual-to-physical mappings, reducing the overhead of virtual memory to less than 1% on average.
Proceedings ArticleDOI
Out-of-order commit processors
TL;DR: A new checkpointing mechanism that is capable of keeping thousands of in-flight instructions at a practically constant cost and a queuing mechanism that takes advantage of the differences in waiting time of the instructions in the flow are proposed.
Proceedings ArticleDOI
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory
Carlos Villavieja,Vasileios Karakostas,Lluis Vilanova,Yoav Etsion,Alex Ramirez,Avi Mendelson,Nacho Navarro,Adrian Cristal,Osman Unsal +8 more
TL;DR: This paper characterize the impact of TLB shoot downs on multiprocessor performance and scalability, and presents the design of a scalable TLB coherency mechanism that couples a shared TLB directory with load/store queue support for lightweight TLB invalidation, and thereby eliminates the need for costly IPIs.
Proceedings ArticleDOI
EazyHTM: eager-lazy hardware transactional memory
Sasa Tomic,Cristian Perfumo,Chinmay Kulkarni,Adria Armejach,Adrian Cristal,Osman Unsal,Tim Harris,Mateo Valero +7 more
TL;DR: A new scalable HTM architecture is shown that performs comparably to the state-of-the-art and can be implemented by minor modifications to the MESI protocol rather than re-engineering it from the ground up and performs on average 7% faster than scalable-TCC.