An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Silicon-based heterostructures have come a long way from the discovery of strain as a new and essential parameter for band structure engineering to the present state of electron and hole mobilities, which surpass those achieved in the traditional material combination by more than an order of magnitude and are rapidly approaching the best III - V heteromaterials. It is the purpose of this article to report on the most recent developments, and the performance level achieved to date in this material system, in a concise and critical manner. The first part of this review is concerned with the structural and electronic properties of the lattice-mismatched Si/SiGe heterostructure. Emphases are put on the effects of strain both on the band structure and on the band offsets, as well as on means to actually control the strain in a stack of heteroepitaxial layers. The second part is dedicated to the transport properties of low-dimensional carrier systems in Si/SiGe and Ge/SiGe heterostructures. The prospects and limitations of the different layer concepts are discussed in terms of scattering mechanisms and experimental results. This part also reviews the most recent magneto-transport experiments on quantum wires and quantum point contacts, which became possible by the enhanced mean free paths in these materials. The third part covers the device aspects of these high-mobility materials, which is of special interest, because silicon-based heterostructures can significantly enhance the performance level of contemporary Si devices without sacrificing the essential compatibility with standard Si technologies. The recent achievements in this application-driven research field, but also the foreseeable problems and limitations, are discussed, and an assessment of the possible role of such heterodevices in future microelectronic circuits is given.

http://iopscience.iop.org/article/10.1088/0268-1242/12/12/001/pdf

High-mobility Si and Ge structures

The decade of the 1990's is an opportune time for scientists and engineers to create cost-effective silicon "superchips" that merge silicon photonics with advanced silicon electronics on a silicon substrate. We can expect significant electrooptical devices from Column IV materials (Si, Ge, C and Sn) for a host of applications. The best devices will use strained-layer epitaxy, doped heterostructures, and bandgap engineering of quantum-confined structures. This paper reviews Si-based photonic components and optoelectronic integration techniques, both hybrid and monolithic. >

Silicon-based optoelectronics

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

The negative bias temperature instability in MOS devices: A review

Random threshold voltage (VM) fluctuation data obtained from multiple fabs, generations and technologies, as well as theoretical / TCAD results are carefully compared using a special normalization method. It is revealed that P-FET fluctuation can be almost fully accounted for by dopant fluctuation regardless of device generations and designs, whereas extra fluctuation mechanism(s) significantly contributes to N-FETs.

Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies

In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

SRAM having an improved capacitor

The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Semiconductor memory device using vertical-channel transistors

Dopant distributions in n-MOSFET structure observed by atom probe tomography.

By i) forming a layered structure of an undoped single crystalline Si layer and single crystalline Si0.8 Ge0.2 mixed crystal layer on an n-Si(100) substrate, a second undoped single crystalline Si layer on it, and a p type hydrogenated amorphous Si1-B CB layer on it, iii) mounting an n-Si0.55 Ge0.40 C0.05 layer on an n-Si(100) substrate and forming a layered structure of an undoped single crystalline Si0.55 Ge0.40 C0.05 layer and Si0.8 Ge0.2 layer, an undoped single crystalline Si0.55 Ge0.40 C0.05 layer, and a p-Si0.55 Ge0.40 C0.05 layer sequentially on it or iv) mounting an n type single crystalline Si layer on an n-Si(100) substrate and forming a layered structure of an undoped single crystalline Si layer and Si0.8 Ge0.1 Sn0.1 layer, an undoped single crystalline Si layer, and a p type single crystalline Si layer sequentially on it, a semiconductor optical device is obtained.

Akio Nishida

Papers

Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies

SRAM having an improved capacitor

Semiconductor memory device using vertical-channel transistors

Dopant distributions in n-MOSFET structure observed by atom probe tomography.

Semiconductor optical device, manufacturing method for the same, and opto-electronic integrated circuit using the same