Showing papers by "Alessandro Trifiletti published in 2006"

Three-phase dual-rail pre-charge logic

Abstract: This paper investigates the design of a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place & route) without any constraint on the routing of the complementary wires. The proposed logic is based on a three phase operation where, in order to obtain a constant energy consumption over the operating cycle, an additional discharge phase is performed after pre-charge and evaluation. In this work, the proposed concept has been implemented as an enhancement of the SABL logic with a limited increase in circuit complexity. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and load capacitances. An improvement in the energy consumption balancing up to 100 times with respect to SABL has been obtained.

Side channel analysis resistant design flow

Abstract: The threat of side-channel attacks (SCA) is of crucial importance when designing systems with cryptographic hardware or software. The FP6-funded project SCARD enhances the typical micro-chip design flow in order to provide a means for designing side-channel resistant circuits and systems. Appropriate SCA-simulation tools and SCA analysis for the designer of secure systems are part of the project goals. We consider these enhancements for traditional design flows of micro-chips as necessary in order to enable the design for the next generation of secure and dependable devices. SCARD is in its final phase, the final result a SCARD chip designed by using the developed design flow is currently implemented.

High-CMRR Current Amplifier Architecture and Its CMOS Implementation

Abstract: A novel current operational amplifier, in which the traditionally adopted input current follower is replaced by an input stage that exhibits current gain and single-input-to-differential-output conversion, is presented. Due to this, increased values of both dc gain and common-mode rejection ratio (CMRR) are obtained in the overall amplifier. A CMOS implementation, along with postlayout simulations, which are in good agreement with expected data, is also included. The proposed design is supplied with 2.5 V, dissipates 0.7 mW, and provides a nominal dc gain, a gain-bandwidth product, and a CMRR (at dc) of 72 dB, 28 MHz, and greater than 100 dB, respectively

A model for the distortion due to switch on-resistance in sample-and-hold circuits

Abstract: A behavioral model of a sample-and-hold circuit is presented, focused on the distortion due to the nonlinear switch on-resistance. A simplified expression for third-order harmonic distortion has been derived, by using a quadratic MOS model where body effect is neglected, and it has been extended to the case of a transmission gate switch. Both the behavioral model and the distortion estimation have been validated by comparison with Cadence simulations, and very low errors have been obtained over a wide range of circuital and signal parameters.

Three-phase dual-rail pre-charge logic

Abstract: This paper investigates the design of a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place & route) without any constraint on the routing of the complementary wires The proposed logic is based on a three phase operation where, in order to obtain a constant energy consumption over the operating cycle, an additional discharge phase is performed after pre-charge and evaluation In this work, the proposed concept has been implemented as an enhancement of the SABL logic with a limited increase in circuit complexity Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and load capacitances An improvement in the energy consumption balancing up to 100 times with respect to SABL has been obtained

A novel concept for stateless random bit generators in cryptographic applications

Abstract: A new, patent pending, concept for a random bit generator, suitable to be integrated in a cryptographic device, is presented. The proposed circuit exploits the relative jitter between two identical ring oscillators sharing the same delay elements and shows several advantages with respect to other oscillator-based generators reported in the technical literature. In particular, the generator is stateless and therefore easily testable accordingly to what is reported in (Bucci, 2005). Moreover, the generation throughput is automatically adapted to the available noise in the circuit thus guaranteeing the statistical quality (minimum entropy) of the generated bits. To validate the proposed circuit, simulation results on a 0.12/spl mu/m CMOS process are reported.

Enhancing power analysis attacks against cryptographic devices

Abstract: A novel current measuring technique is introduced which promises to substantially enhance power analysis attacks against cryptographic co-processors. The proposed technique exploits an active circuit to measure the instantaneous current consumption of a device under attack while supplying, at the same time, the device with a stable voltage. Higher gain-bandwidth product, higher sensitivity and lower insertion error are the main advantages with respect to a resistor-based measurement. Experimental results when the proposed circuit is used to measure the current consumption of an FPGA are reported and the achievable advantage in terms of sensitivity is discussed too.

Discussion and new proofs of the conditional stability criteria for multidevice microwave amplifiers

Abstract: In the design of microwave multidevice amplifiers, criteria ensuring conditional stability allow a better trade-off between performance and stability to be obtained with respect to unconditional stability criteria. Previous results concerning conditional stability of linear two-ports are discussed, and new proofs of the conditional stability criterion ensuring stability for all the values of input and output terminations located in circular regions of the Smith chart are provided. By following the proposed proofs, it is shown for the first time that necessary and sufficient conditions for conditional stability can be ascertained by means of a single parameter. The overall stability factors are directly obtained starting from Ohtomo's proviso on unconditional stability. Procedures to apply the conditional stability criterion to the synthesis of multidevice amplifiers are also outlined and illustrated by means of a case study concerning the design of a four-stage distributed amplifier in the 1-10 GHz frequency band.

Stability Criterion for Two-Port Network With Input and Output Terminations Varying in Elliptic Regions

Abstract: New criteria to check the conditional stability of microwave amplifiers with input and output terminations varying in prespecified elliptic regions surrounding complex nominal values are proposed. Necessary and sufficient conditions are provided in terms of the immittance parameters lambdaij (i.e., zij, yij, gij, or hij): these conditions can be implemented in commercial computer-aided design tools and are suitable to be used as design goals within optimization routines. Since elliptic shapes accurately fit the real variability region of input and output terminations, the proposed criterion allows to impose stability in the actual tolerance range of terminations and therefore to improve the tradeoff between performance and stability under termination variations

Inverting closed-loop amplifier architecture with reduced gain error and high input impedance

Abstract: We propose an inverting closed-loop amplifier architecture providing high input impedance and a theoretically zero gain error, without requiring infinitely large loop gain. The architecture is based on two nested amplifiers closed in feedback through a resistive network. A straightforward CMOS implementation is also given. Simulations using a 0.35-/spl mu/m CMOS process are found in agreement with expected results. Monte Carlo simulations have also shown the robustness of the proposed approach against process tolerances.

Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis

Abstract: A distance-dependent non-linear statistical model of the active part of a very short-length HEMT-based MMIC, expressed in terms of principal components, is presented. A statistical model has been extracted for 0.1 /spl mu/m GaAs HEMT devices and MMIC's. Validation of the model is presented, based on principal component analysis and statistical hypothesis testing.