scispace - formally typeset
Search or ask a question

Showing papers by "Alina Deutsch published in 2001"


Journal ArticleDOI
01 Apr 2001
TL;DR: This paper reviews the status of present day on-chip wiring design methodologies and understanding and design guidelines are given for using modeling and simulation techniques that have been previously used for package interconnections to teach designers how to make better use of available technologies.
Abstract: This paper reviews the status of present day on-chip wiring design methodologies and understanding. A brief explanation is given of the fundamental transmission-line properties that should be considered for accurate prediction of crosstalk, common-mode noise and clock skew. The deficiencies of RC-circuit representation are highlighted and design guidelines are given for using modeling and simulation techniques that have been previously used for package interconnections. Such techniques are believed to teach designers how to make better use of available technologies and help them architect systems that operate with many-GHz clock rates.

222 citations


Journal ArticleDOI
TL;DR: This paper compares the major classes of chip-to-chip and on-chips interconnections used in high-performance computers and communication systems and reviews their electrical characteristics.
Abstract: This paper compares the major classes of chip-to-chip and on-chips interconnections used in high-performance computers and communication systems and reviews their electrical characteristics. Measurement results of dielectric loss are shown and the attenuation is compared for printed-circuit-board, glass-ceramic, thin-film, and on-chip wiring. Simulation results are shown with representative driver and receiver circuits, guidelines are given for when losses are significant, and predictions are made for the sustainable bandwidths on useful wiring lengths.

50 citations


Proceedings ArticleDOI
06 May 2001
TL;DR: In this paper, a coupling noise evaluation of a high performance S/390 microprocessor using a full chip RLC extraction and simulation process is presented, in terms of algorithms and procedures used to account for the frequency dependent RLC effects in a manner that allow a full-chip noise evaluation.
Abstract: A coupling noise evaluation of a high performance S/390 microprocessor using a full chip RLC extraction and simulation process is presented. Review of on-chip wiring guidelines with respect to the inaccuracies of an RC coupling evaluation for known net topologies is discussed in terms of tool requirements for full-chip noise evaluation which include inductive coupling effects. The extraction and simulation approach is described in terms of algorithms and procedures used to account for the frequency dependent RLC effects in a manner that allow a full chip noise evaluation. Results are presented which compare noise amplitude differences between RC and R(f)L(f)C evaluations for the wiring data of an S/390 microprocessor as well as pertinent statistics such as run times and memory usage.

12 citations