Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

A physics-based 2-D analytical model for surface potential, electric field, drain current, subthreshold swing (SS) and threshold voltage of dual-material (DM) double-gate tunnel FETs (DG TFETs) with SiO2/HfO2 stacked gate-oxide structure has been developed in this paper. The parabolic-approximationtechnique, with suitable boundary conditions, has been used to solve Poisson’s equation in the channel region. Channel potential model is used to develop electric field expression. The drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the channel thickness. Threshold voltage has been extracted by maximum transconductance method. The proposed model also demonstrates that the proper choice of work function for both the latterly contacting gate electrode (near the source and drain) materials which can give better results in terms of input-output characteristics, SS, and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ than the conventional TFET devices. Although the proposed model has been primarily developed for Si-channel-based DM DG TFET devices, however, the model has also been shown to be applicable for other materials like SiGe (indirect bandgap) and InAs channel-based TFET structures. The results of the proposed model have been validated against the TCAD simulation results obtained by using SILVACO ATLAS device simulation software.

2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO 2 /HfO 2 Stacked Gate-Oxide Structure

We propose an empirical simulation model for p-channel floating-gate MOS synapse transistors. Since our model requires only a transistor and controlled sources, and does not use the MOSFET's channel potential in its description, we can apply the model in any SPICE circuit simulator. The model parameters derive from simple oxide-current measurements. We present fit parameters from MOSFETs with 70 /spl Aring/ oxides in a 0.35 /spl mu/m process, and verify our model by comparing simulations and measured data from a capacitive-feedback CMOS operational amplifier.

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A simulation model for floating-gate MOS synapse transistors

In this paper, we investigate a polarity controlled electrically doped tunnel FET (ED-TFET) based on the bandgap engineering for analog/RF applications. The proposed device exhibits a heavily doped n-type Si-channel with two distinctive gate: 1) control gate (CG) and 2) polarity gate (PG). First, the work function of 4.72 eV is considered for CG and PG to convert the layer beneath CG and PG of intrinsic type. Further, a bias of −1.2 V is applied at PG terminal to induce a p+ region, so that, it follows the similar trend as like a n+-i-p+ gated structure of conventional TFET. To improve the ON-state current of the proposed device, we investigate an interfacing of III–V with IV group material for heterojunction. It shows higher ON-state current in the order of $10^{-4}$ A/ $\mu \text{m}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio (in the order of $10^{12}$ ) at ${V}_{\sf DS} = 0.7$ V. Further, its higher transconductance ${g} _{m}\approx 1.02$ mS and different RF performance parameters in the range of terahertz, enables its potential for analog/RF applications. However, linearity parameters are analyzed to give the assurance of the device for high-frequency applications. Moreover, a nonquasi-static RF model is adopted to analyze the behavior of the proposed ED-TFET in high frequency region. Based on this, the small-signal parameters were extracted and verified upto 500 GHz. The modeled result shows excellentmatching with the Y-parameters upto 500 GHz.

Design and Analysis of Polarity Controlled Electrically Doped Tunnel FET With Bandgap Engineering for Analog/RF Applications

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In this paper, a new 2-D analytical model for the surface potential of a dual-metal-gate double-gate tunnel field-effect transistor is presented. It takes into account the effects of the drain and gate voltages, gate metal work function, insulator thickness, silicon film thickness, and source and drain depletions. The surface potential thus obtained is used to calculate the tunneling widths at both the source and drain junctions, which are subsequently used as the limits for the integration of the band-to-band generation rate in order to arrive at the tunneling current. In this paper, the band-to-band tunneling is considered to take place through both the source as well as the drain depletion regions. Our model accounts for the variable drain doping through a fitting function, which is postulated based on the theory of generation current, and the results have been found to predict the correct ambipolar behavior of the tunneling field-effect transistors. The results of our model, both for the surface potential and the tunneling current, match very well with those obtained through the TCAD simulations.

Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs

In this paper, we present an analytical model for the drain current of a double-gate tunnel field-effect transistor (DGTFET), derived using the pseudo-2-D Poisson’s equation in order to obtain the surface potential in both the channel and the source regions. We have proposed a new model for the surface potential when the channel is under accumulation, and have analytically modeled source depletion as well. We have also proposed a modification in the existing model for the band-to-band tunneling, by taking into account the change in the carrier momentum vector during its transit from the source valence band to the channel conduction band. Another important contribution of our work is the prediction of zero drain current at zero drain bias, which is physically modeled for the first time. The negative conductance region for low gate bias is also modeled for the first time using an empirical formulation, without using any fitting parameter. Extensive TCAD simulations were performed in order to prove the veracity of our model with respect to drain bias, gate bias, substrate doping, and metal work function, and the match of our model results with the simulated data was found to be excellent.

Analytical Drain Current Modeling of Double-Gate Tunnel Field-Effect Transistors

In this paper, we present a new and improved substrate current model for submicron MOSFETs, which uses a simple analytical approximation of the ionization length near the drain, which in turn is based on a calculation of the electric field distribution near the drain region. The simulation results from our models for the ionization length as well as the substrate current are compared with the experimental results reported in literature, and a good match between the two is obtained.

A new substrate current model for submicron MOSFETs

In this paper, we present a completely analytical model for the gate tunneling current, which can be used to get a first-order estimate of this parameter in present-generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. The model has been developed from first principles, and it does not use any empirical fitting and/or correction parameters. It takes into account the quantization of the electron energy levels within the inversion layer of a MOSFET, which behaves similar to a potential well. Several interesting simplifications regarding this well structure have been made, and all these assumptions have been rigorously justified, both based on physical arguments as well as through numerical quantifications. An extremely interesting and important outcome of this procedure is a nonzero value of the wavefunction at the semiconductor-insulator interface, which is physically justified, however, contrary to what other existing literatures in this area assume. This procedure also led to a closed-form analytical expression for the inversion layer thickness. The interface wavefunction was used, in association with the tunneling probability through the gate oxide, and the carriers in transit model in the gate metal, to find the resultant gate tunneling current density as a function of the applied gate-to-body voltage. The results obtained from our simple and completely analytical model were compared with the experimental results reported in the literature, and the match is found to be excellent for varying oxide thicknesses and substrate doping concentrations, which justifies the authenticity of the model developed in this work here.

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides

Here, we report a unified analytical model for the 2-D electron gas density ( ${n}_{S}$ ) in AlGaN/GaN HEMTs, considering the carriers induced in the AlGaN layer ( ${n}_{B}$ ) to satisfy charge balance at high gate bias. To extend the validity of our model for gate voltages below the off voltage, we have merged a popular subthreshold model to our model using an interpolation function. Our model for ${n}_{B}$ is fully analytical, without any explicit dependence on ${n}_{S}$ , and is a function only of the gate voltage, which to the best of our knowledge, is the first such report. The model results show a very good match with published results and experimental data reported in the literature. These models are subsequently used in a charge-based drain current model, developed under the drift-diffusion framework. In order to make our model valid for small-dimension devices, several second-order effects have been included in our drain current model. The model results for the drain current show an excellent match with the experimental data reported in the literature, for channel length varying from $1~\mu \text{m}$ to 125 nm. Also, it shows the first-order continuity of the drain current with respect to the bias voltages, thus making it suitable for use in circuit simulators.

Aloke K. Dutta

Papers

Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs

Analytical Drain Current Modeling of Double-Gate Tunnel Field-Effect Transistors

A new substrate current model for submicron MOSFETs

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides

Analytical Models for the 2DEG Density, AlGaN Layer Carrier Density, and Drain Current for AlGaN/GaN HEMTs