A
Amirali Boroumand
Researcher at Carnegie Mellon University
Publications - 24
Citations - 2017
Amirali Boroumand is an academic researcher from Carnegie Mellon University. The author has contributed to research in topics: Dram & Cache coherence. The author has an hindex of 14, co-authored 24 publications receiving 1320 citations. Previous affiliations of Amirali Boroumand include Sharif University of Technology.
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Proceedings ArticleDOI
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology
Vivek Seshadri,Donghyuk Lee,Thomas Mullins,Hasan Hassan,Amirali Boroumand,Jeremie S. Kim,Michael Kozuch,Onur Mutlu,Phillip B. Gibbons,Todd C. Mowry +9 more
TL;DR: Ambit is proposed, an Accelerator-in-Memory for bulk bitwise operations that largely exploits existing DRAM structure, and hence incurs low cost on top of commodity DRAM designs (1% of DRAM chip area).
Proceedings ArticleDOI
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks
Amirali Boroumand,Saugata Ghose,Youngsok Kim,Rachata Ausavarungnirun,Eric Shiu,Rahul Thakur,Dae Hyun Kim,Aki Kuusela,Allan Knies,Parthasarathy Ranganathan,Onur Mutlu +10 more
TL;DR: This work comprehensively analyzes the energy and performance impact of data movement for several widely-used Google consumer workloads, and finds that processing-in-memory (PIM) can significantly reduceData movement for all of these workloads by performing part of the computation close to memory.
Proceedings ArticleDOI
Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation
Kevin Hsieh,Samira Khan,Nandita Vijaykumar,Kevin K. Chang,Amirali Boroumand,Saugata Ghose,Onur Mutlu +6 more
TL;DR: The In-Memory PoInter Chasing Accelerator (IMPICA), which leverages the logic layer within 3D-stacked memory for linked data structure traversal and addresses the key challenges of how to achieve high parallelism in the presence of serial accesses in pointer chasing, and how to effectively perform virtual-to-physical address translation on the memory side without requiring expensive accesses to the CPU's memory management unit.
Journal ArticleDOI
Fast Bulk Bitwise AND and OR in DRAM
Vivek Seshadri,Kevin Hsieh,Amirali Boroumand,Donghyuk Lee,Michael Kozuch,Onur Mutlu,Phillip B. Gibbons,Todd C. Mowry +7 more
TL;DR: This work proposes a new and simple mechanism to implement bulk bitwise AND and OR operations in DRAM, which is faster and more efficient than existing mechanisms.
Journal ArticleDOI
LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory
Amirali Boroumand,Saugata Ghose,Minesh Patel,Hasan Hassan,Brandon Lucia,Kevin Hsieh,Malladi Krishna T,Zheng Hongzhong,Onur Mutlu +8 more
TL;DR: It is found that LazyPIM improves average performance across a range of PIM applications by 49.1 percent over the best prior approach, coming within 5.5 percent of an ideal PIM mechanism.