algorithmics and modular computations, Theory of Codes and Cryptography (3).From an analytical 1. RE Blahut. Theory and practice of error control codes. eecs.uottawa.ca/∼yongacog/courses/coding/ (3) R.E. Blahut,Theory and Practice of Error Control Codes, Addison Wesley, 1983. QA 268. Cached. Download as a PDF 457, Theory and Practice of Error Control CodesBlahut 1984 (Show Context). Citation Context..ontinued fractions.

Theory and practice of error control codes

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.

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50 Years of CORDIC: Algorithms, Architectures, and Applications

The increasing wireless data traffic demands have driven the need to explore suitable spectrum regions for meeting the projected requirements. In the light of this, millimeter wave (mmWave) communication has received considerable attention from the research community. Typically, in fifth generation (5G) wireless networks, mmWave massive multiple-input multiple-output (MIMO) communications is realized by the hybrid transceivers which combine high dimensional analog phase shifters and power amplifiers with lower-dimensional digital signal processing units. This hybrid beamforming design reduces the cost and power consumption which is aligned with an energy-efficient design vision of 5G. In this paper, we track the progress in hybrid beamforming for massive MIMO communications in the context of system models of the hybrid transceivers’ structures, the digital and analog beamforming matrices with the possible antenna configuration scenarios and the hybrid beamforming in heterogeneous wireless networks. We extend the scope of the discussion by including resource management issues in hybrid beamforming. We explore the suitability of hybrid beamforming methods, both, existing and proposed till first quarter of 2017, and identify the exciting future challenges in this domain.

https://biblio.ugent.be/publication/8585223/file/8585225.pdf

A Survey on Hybrid Beamforming Techniques in 5G: Architecture and System Model Perspectives

MPEG-4 is the multimedia standard for combining interactivity, natural and synthetic digital video, audio and computer-graphics Typical applications are: internet, video conferencing, mobile videophones, multimedia cooperative work, teleteaching and games With MPEG-4 the next step from block-based video (ISO/IEC MPEG-1, MPEG-2, CCITT H261, ITU-T H263) to arbitrarily-shaped visual objects is taken This significant step demands a new methodology for system analysis and design to meet the considerably higher flexibility of MPEG-4 Motion estimation is a central part of MPEG-1/2/4 and H261/H263 video compression standards and has attracted much attention in research and industry, for the following reasons: it is computationally the most demanding algorithm of a video encoder (about 60-80% of the total computation time), it has a high impact on the visual quality of a video encoder, and it is not standardized, thus being open to competition Algorithms, Complexity Analysis, and VLSI Architectures for MPEG-4 Motion Estimation covers in detail every single step in the design of a MPEG-1/2/4 or H261/H263 compliant video encoder: Fast motion estimation algorithms Complexity analysis tools Detailed complexity analysis of a software implementation of MPEG-4 video Complexity and visual quality analysis of fast motion estimation algorithms within MPEG-4 Design space on motion estimation VLSI architectures Detailed VLSI design examples of (1) a high throughput and (2) a low-power MPEG-4 motion estimator Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation is an important introduction to numerous algorithmic, architectural and system design aspects of the multimedia standard MPEG-4 As such, all researchers, students and practitioners working in image processing, video coding or system and VLSI design will find this book of interest

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

With the exponential growth of the data traffic in wireless communication systems, terahertz (THz) frequency band is envisioned as a promising candidate to support ultra-broadband for future beyond fifth generation (5G), bridging the gap between millimeter wave (mmWave) and optical frequency ranges. The purpose of this paper is to provide a comprehensive literature review on the development towards THz communications and presents some key technologies faced in THz wireless communication systems. Firstly, despite the substantial hardware problems that have to be developed in terms of the THz solid state superheterodyne receiver, high speed THz modulators and THz antennas, the practical THz channel model and the efficient THz beamforming are also described to compensate for the severe path attenuation. Moreover, two different kinds of lab-level THz communication systems are introduced minutely, named a solid state THz communication system and a spatial direct modulation THz communication system, respectively. The solid state THz system converts intermediate frequency (IF) modulated signal to THz frequency while the direct modulation THz system allows the high power THz sources to input for approving the relatively long distance communications. Finally, we discuss several potential application scenarios as well as some vital technical challenges that will be encountered in the future THz communications.

A survey on terahertz communications

Three-dimensional network-on-chip (3D NoC), the combination of NoC and die-stacking 3D IC technology, is motivated to achieve lower latency, lower power consumption, and higher network bandwidth. However, the length of heat conduction path and power density per unit area increase as more dies stack vertically. Routers of NoC have comparable thermal impact as processors and contributes significant to overall chip temperature. High temperature increases the vulnerability of the system in performance, power, reliability, and cost. To ensure both thermal safety and less performance impact from temperature regulation, we propose a traffic- and thermal-aware run-time thermal management (RTM) scheme. The scheme is composed of a proactive downward routing and a reactive vertical throttling. Based on a validated traffic-thermal mutual-coupling co-simulator, our experiments show the proposed scheme is effective. The proposed RTM can be combined with thermal-aware mapping techniques to have potential for higher run-time thermal safety.

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Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems

This paper presents a multi-mode decoder design for Quasi-Cyclic LDPC codes for Mobile WiMAX system. This chip can be operated in 19 kinds of modes specified in Mobile WiMAX system, including block sizes of 576,..., 2304. There are four proposed design techniques: reordering of the base matrix, overlapped operations of main computational units, early termination strategy and multi-mode design strategy. Based on overlapped decoding mechanism, the decoding latency can be reduced to 68.75% of non-overlapped method, and the hardware utilization ratio can be enhanced from 50% to 75%. Besides, the proposed early termination strategy can dynamically adjust the number of iterations when dealing with communication channels of different SNR values. The proposed multi-mode LDPC decoder design is implemented and fabricated in TSMC 0.13 mum 1.2 V 1P8M CMOS technology. The maximum operating frequency is measured 83.3 MHz and the corresponding power dissipation is 52 mW. The core size is 4.45 mm2 and the die area only occupies 8.29 mm2.

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An 8.29 mm $^{2}$ 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 $\mu$ m CMOS Process

The CORDIC algorithm is a well-known iterative method for the computation of vector rotation. However, the major disadvantage is its relatively slow computational speed. For applications that require forward rotation (or vector rotation) only, we propose a new scheme, the modified vector rotational CORDIC (MVR-CORDIC) algorithm, to improve the speed performance of CORDIC algorithm. The basic idea of the proposed scheme is to reduce the iteration number directly while maintaining the SQNR performance. This can be achieved by modifying the basic microrotation procedure of CORDIC algorithm. Meanwhile, three searching algorithms are suggested to find the corresponding directional and rotational sequences so as to obtain the best SQNR performance. Three SQNR performance refinement schemes are also suggested in this paper. Namely, the selective prerotation scheme, selective scaling scheme, and iteration-tradeoff scheme. They can reduce and balance the quantization errors encountered in both microrotation and scaling phases so as to further improve the overall SQNR performance. Then, by combining these three refinement schemes, we provide a systematic design flow as well as the optimization procedure in the application of MVR-CORDIC algorithm. Finally, we present two VLSI architectures for the MVR-CORDIC algorithm. It shows that by using the proposed MVR-CORDIC algorithm, we can save 50% execution time in the iterative CORDIC structure, or 50% hardware complexity in the parallel CORDIC structure compared with the conventional CORDIC scheme.

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Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture

This paper presents an efficient binomial IP mapping and optimization algorithm (BMAP) to reduce the hardware cost of on-chip network (OCN) infrastructure. The complexity of BMAP is O(N2log(N)). Based on our OCN system synthesis flow, the proposed algorithm provides more economic network component mapping in comparison with traditional OCN mapping algorithm. The experimental result shows total traffic on network is reduced by 37% and average network hop count is reduced by 46%. With further optimization, the hardware efficiency is enhanced therefore the total hardware cost of network infrastructure is reduced to 51%~85%

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A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network

The coordinate rotational digital computer (CORDIC) algorithm is a well-known iterative arithmetic for performing vector rotations in many digital signal processing (DSP) applications. However, the large number of iteration is a major disadvantage of this algorithm for its speed performance. Many researchers have proposed schemes to reduce the number of iterations. Nevertheless, in performing the existing CORDIC algorithms, the norm of the vector is usually enlarged so that extra scaling operations are required to deliver the normalized output. In this paper, we merge the two operation phases (microrotations and scaling phases) and propose a new vector rotational scheme called mixed-scaling-rotation coordinate rotational digital computer (MSR-CORDIC) algorithm. It can eliminate the overhead of the scaling operations that are inevitable in existing CORDIC algorithms; hence, it can significantly reduce the total iteration number so as to improve the speed performance. The proposed MSR-CORDIC can be applied to DSP applications, in which the rotational angles are known in advance [e.g., twiddle factor in fast Fourier transform (FFT) processor designs]. Moreover, most CORDIC algorithms generally suffer from the roundoff noise in the fixed-wordlength implementations. We also propose two schemes to control and reduce the impairment. Our simulation results show that the MSR-CORDIC algorithm can enhance the signal-to-quantization-noise ratio (SQNR) performance by controlling the internal dynamic range. We also investigate the first- and second-order statistical properties, including the mean and variance of the SQNR. Simulation results show that the MSR-CORDIC can enhance SQNR performance of both first- and second-order statistical properties. At the VLSI architecture level, we proposed a generalized MSR-CORDIC engine for the tradeoff between hardware complexity and quantization error performance. It can further reduce the hardware complexity when compared with the newly proposed extend elementary angle set CORDIC algorithm . The MSR-CORDIC scheme has been applied to a variable-length FFT processor design , and results in significant hardware reduction in implementing the twiddle factor operations.

/pdf/mixed-scaling-rotation-cordic-msr-cordic-algorithm-and-23x20d1ic8.pdf

An-Yeu Wu

Papers

Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems

An 8.29 mm $^{2}$ 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 $\mu$ m CMOS Process

Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture

A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network

Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications