A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33fJ/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3ppm/°C is achieved without the need for calibration.

A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

This paper reports the state of art in a variety of pressure and the detailed study of various matrix based pressure sensors. The performances of the bridges, buildings, etc. are threatened by earthquakes, material degradations, and other environmental effects. Structural health monitoring (SHM) is crucial to protect the people and also for assets planning. This study is a contribution in developing the knowledge about self-sensing smart materials and structures for the construction industry. It deals with the study of self-sensing as well as mechanical and electrical properties of different matrices based on pressure sensors. The relationships among the compression, tensile strain, and crack length with electrical resistance change are also reviewed.

https://link.springer.com/content/pdf/10.1007%2Fs13320-017-0419-z.pdf

Review on pressure sensors for structural health monitoring

This paper presents a novel CMOS integrated capacitive pressure sensor, fabricated in silicon–germanium microelectromechanical systems (SiGeMEMS) process, with the sensor held and linked to the CMOS beneath. The CMOS process houses the on-chip signal conditioning circuit. The superior stress–strain behavior of polycrystalline silicon–germanium (poly-SiGe) is effectively utilized to develop and characterize the structure of the pressure sensor diaphragm element. The edge-clamped elliptic structured diaphragm employs semimajor axis L-shaped clamp springs to yield high sensitivity, wide dynamic range, and good linearity. To maximize the center deflection of the diaphragm, a stem structure is designed to transfer the entire stress on to the diaphragm center. The signal conditioning circuit is fabricated in a 0.18 $\mu $ m TSMC CMOS process (forming the host substrate for the SiGe-MEMS sensor) and achieves a high overall gain of 100 dB for the sensor readout. Experimental results indicate a high sensitivity of $\sim 0.12$ mV/hPa (at 1.4 V supply), along with a nonlinearity of $\sim 1$ % for the full-scale range of applied pressure load. The diaphragm with a wide dynamic range of 100–1000 hPa is stacked on top of the CMOS circuitry. The piggyback structure reduces the combined sensor and conditioning circuit implementation area of the intelligent sensor chip to $\sim 750~\mu $ m $\times 750~\mu $ m. The major and minor axis dimensions of the sensor were 485 $\mu $ m and 280 $\mu $ m, respectively. The device achieved wider low-pressure sensing range at lower supply voltage compared with commercial pressure sensors.

Elliptic Diaphragm Capacitive Pressure Sensor and Signal Conditioning Circuit Fabricated in SiGe CMOS Integrated MEMS

In this study, a local positive feedback technique is proposed to enhance the performance of the folded cascode (FC) operational transconductance amplifier (OTA) when working in its saturation region. The enhanced FC-OTA has a higher gain bandwidth (GBW), higher DC gain and higher slew rate (SR) over its conventional counterparts and popular recycling FC-OTAs. The proposed enhanced FC-OTA is implemented by reusing the current generated by the input transistors through the proposed local positive feedback loop to provide additional transconductance and negative resistance. It is then fabricated with SMIC 180nm process. To verify the effectiveness of the proposed FC-OTA performance enhancement strategy, extensive mathematical analysis, small-/large-signal stability analysis, simulation and experimentation are thoroughly investigated in this study. Simulation and experimental results agree well with the theoretical analysis and the expected performances, which corroborates the control design.

A Robust Local Positive Feedback Based Performance Enhancement Strategy for Non-Recycling Folded Cascode OTA

High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges.We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling.We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful”requirements for the various enabling dielectric hard mask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements.We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.© 2019 The Electrochemical Society.

https://iopscience.iop.org/article/10.1149/2.0161910jss/pdf

Review—Beyond the highs and lows: A perspective on the future of dielectrics research for nanoelectronic devices

The requirement of high gain and low noise for sensor readout instrumentation is addressed in this brief. A novel current cross-mirroring technique is employed to enhance the small signal current of the proposed quadruply split cross-driven doubly recycled folded cascode (RFC) operational transconductance amplifier. The small signal current is increased by using split devices and two mirroring ratios (F and H), resulting in a double (or higher) transconductance $(g_{{m}})$ value and, hence, very high single-stage gain. Four fractionally split input differential pair transistors are utilized for achieving the further increase in gain without compromising the unity-gain–bandwidth (UGBW). Bias current splitting yielded a better slew rate and faster settling time. Results using the 130-nm IBM CMOS technology demonstrated a gain of 75 dB for the single-stage fully differential mode of the chopper-stabilized proposed enhanced- $g_{{m}}$ RFC. A significant open-loop UGBW of 166 MHz was also achieved in association with an 82.5° phase margin. In addition, an input-referred noise level as low as 48.3 $\mu\text{Vrms}$ was also achieved. A sensor readout circuit using the proposed instrumentation amplifier was verified using capacitive microsensors cofabricated on the 130-nm CMOS process, demonstrating wide dynamic range and high linearity.

Quadruply Split Cross-Driven Doubly Recycled $g_{{m}}$ -Doubling Recycled Folded Cascode for Microsensor Instrumentation Amplifiers

Monolithic post-processing and characterization of CMOS MEMS capacitive absolute pressure sensors co-integrated on an 8-metal BEOL (back-end-of-line) 130 nm CMOS device is reported in this paper. An optimized foundry compatible etch process for an IBM CMOS fabricated top triple layered passivation is discussed. A mixture of wet and plasma dry etch process is proposed for both an elliptic and a rectangular structured pressure sensor capacitor. Lateral 125 μm stiction free etch from opposite sides was performed successfully for the monolithically integrated diaphragms on the 130 nm CMOS platform. Low power inductive coupled plasma using CHF 3 gas along with high RF bias power is utilized to increase lateral etch rate compared to vertical etch rate. Mechanical and electrical characterization results indicate a successful etch of the triple layer passivation and the sacrificial oxide. Sensitivities of the fluorosilicate sealed absolute pressure sensors were measured to be 0.07 mV/Pa and 0.05 mV/Pa for the elliptic and rectangular element, respectively. In addition, the linear capacitive transduction dynamic range was found to be 0.32 pF and 0.23 pF, respectively, for the elliptic and rectangular element (for 80 hPa pressure variation).

Release etching and characterization of MEMS capacitive pressure sensors integrated on a standard 8-metal 130 nm CMOS process

Post-processing and performance analysis of BEOL integrated MEMS pressure sensor capacitors in 8-metal 130nm CMOS

A novel CMOS integrated Micro-Electro-Mechanical capacitive pressure sensor in SiGe MEMS (Silicon Germanium Micro-Electro-Mechanical System) process is designed and analyzed Excellent mechanical stress---strain behavior of Polycrystalline Silicon Germanium (Poly-SiGe) is utilized effectively in this MEMS design to characterize the structure of the pressure sensor diaphragm element The edge clamped elliptic structured diaphragm uses semi-major axis clamp springs to yield high sensitivity, wide dynamic range and good linearity Integrated on-chip signal conditioning circuit in 018 μm TSMC CMOS process (forming the host substrate base for the SiGe MEMS) is also implemented to achieve a high overall gain of 102 dB for the MEMS sensor A high sensitivity of 017 mV/hPa (@14 V supply), with a non linearity of around 1 % is achieved for the full scale range of applied pressure load The diaphragm with a wide dynamic range of 100---1,000 hPa stacked on top of the CMOS circuitry, effectively reduces the combined sensor and conditioning implementation area of the intelligent sensor chip

Ananiah Durai Sundararajan

Papers

Elliptic Diaphragm Capacitive Pressure Sensor and Signal Conditioning Circuit Fabricated in SiGe CMOS Integrated MEMS

Quadruply Split Cross-Driven Doubly Recycled $g_{{m}}$ -Doubling Recycled Folded Cascode for Microsensor Instrumentation Amplifiers

Release etching and characterization of MEMS capacitive pressure sensors integrated on a standard 8-metal 130 nm CMOS process

Post-processing and performance analysis of BEOL integrated MEMS pressure sensor capacitors in 8-metal 130nm CMOS

CMOS integrated elliptic diaphragm capacitive pressure sensor in SiGe MEMS