Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Fast parallel algorithms for short-range molecular dynamics

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

/pdf/a-survey-of-research-and-practices-of-network-on-chip-2rc0mlsrfq.pdf

A survey of research and practices of Network-on-chip

: The unpolarized absorption and circular dichroism spectra of the fundamental vibrational transitions of the chiral molecule, 4-methyl-2-oxetanone, are calculated ab initio. Harmonic force fields are obtained using Density Functional Theory (DFT), MP2, and SCF methodologies and a 5S4P2D/3S2P (TZ2P) basis set. DFT calculations use the Local Spin Density Approximation (LSDA), BLYP, and Becke3LYP (B3LYP) density functionals. Mid-IR spectra predicted using LSDA, BLYP, and B3LYP force fields are of significantly different quality, the B3LYP force field yielding spectra in clearly superior, and overall excellent, agreement with experiment. The MP2 force field yields spectra in slightly worse agreement with experiment than the B3LYP force field. The SCF force field yields spectra in poor agreement with experiment.The basis set dependence of B3LYP force fields is also explored: the 6-31G* and TZ2P basis sets give very similar results while the 3-21G basis set yields spectra in substantially worse agreements with experiment. jg

Ab initio calculation of vibrational absorption and circular dichroism spectra using density functional force fields

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

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Design Of Analog Cmos Integrated Circuits

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

/pdf/performance-evaluation-and-design-trade-offs-for-network-on-2r2qk1xk70.pdf

Performance evaluation and design trade-offs for network-on-chip interconnect architectures

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

System-on-Chip: Reuse and Integration

System on Chip (SoC) design in the forthcoming billion transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks Some of the main problems in the ultra deep sub micron technologies characterized by gate lengths in the range of 50-100 nm arise from non-scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues, and difficulties associated with non-scalable bus-based functional interconnect These problems are addressed in this paper by introducing a new design methodology A switch-based network-centric architecture to interconnect IP blocks is proposed We introduce a butterfly fat tree architecture as an overall interconnect template In this new interconnect architecture, switches are used to transfer data between IP blocks To reduce overall latency and hardware overhead, wormhole routing is adopted The proposed switch architecture supports this routing method Initial implementation of the switch reveals that the total switch area is expected to amount to less than 2% of a large SoC

/pdf/design-of-a-switch-for-network-on-chip-applications-2ovmai4gd3.pdf

Design of a switch for network on chip applications

For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.

Design, synthesis, and test of networks on chips

We present a comprehensive analysis of jitter causes and types, and develops accurate jitter models for design and test of high-speed interconnects. The recent deployment of gigabit-per-second (Gbps) serial I/O interconnects aims at overcoming data transfer bottlenecks resulting from the limited ability to increase chip pin counts in parallel bus architectures. The traditional measure of a communication link's performance has been its associated bit error rate (BER), which is the ratio of the number of bits received in error to the total number of bits transmitted. When data rates increase, jitter magnitude and signal amplitude noise must decrease to maintain the same BER. As data rates exceed 1 Gbps, a slight increase in jitter or amplitude noise has a far greater effect on the BER.

Andre Ivanov

Papers

Performance evaluation and design trade-offs for network-on-chip interconnect architectures

System-on-Chip: Reuse and Integration

Design of a switch for network on chip applications

Design, synthesis, and test of networks on chips

Jitter models for the design and test of Gbps-speed serial interconnects