C
C. Grecu
Researcher at University of British Columbia
Publications - 49
Citations - 2787
C. Grecu is an academic researcher from University of British Columbia. The author has contributed to research in topics: Network on a chip & System on a chip. The author has an hindex of 22, co-authored 49 publications receiving 2726 citations. Previous affiliations of C. Grecu include École Polytechnique Fédérale de Lausanne & Massachusetts Institute of Technology.
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Journal ArticleDOI
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
TL;DR: This paper develops a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures and explores design trade-offs that characterize the NoC approach and obtains comparative results for a number of common NoC topologies.
Journal ArticleDOI
System-on-Chip: Reuse and Integration
Resve A. Saleh,Steven J. E. Wilton,Shahriar Mirabbasi,Alan J. Hu,Mark R. Greenstreet,Guy G.F. Lemieux,Partha Pratim Pande,C. Grecu,Andre Ivanov +8 more
TL;DR: This paper focuses on the reuse and integration issues encountered in this paradigm shift in system-on-chip (SoC) design, which includes connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network- on- chip (NoC) architectures.
Proceedings ArticleDOI
Design of a switch for network on chip applications
TL;DR: A switch-based network-centric architecture to interconnect IP blocks is proposed with a butterfly fat tree architecture as an overall interconnect template and wormhole routing is adopted to reduce overall latency and hardware overhead.
Journal ArticleDOI
Design, synthesis, and test of networks on chips
TL;DR: The latest NoC architectures, methods, and tools are surveyed and what must happen to make NoCs part of a viable future is shown.
Proceedings ArticleDOI
BIST for network-on-chip interconnect infrastructures
TL;DR: A novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips using a high-level fault model that accounts for crosstalk effects due to inter-wire coupling.