Journal ArticleDOI
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
TLDR
This paper develops a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures and explores design trade-offs that characterize the NoC approach and obtains comparative results for a number of common NoC topologies.Abstract:
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.read more
Citations
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Journal ArticleDOI
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
TL;DR: This paper provides a general description of NoC architectures and applications and enumerates several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation.
Journal ArticleDOI
FPGAs in Industrial Control Applications
TL;DR: The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications and two short case studies of Neural Network control systems designs targeting FPGAs are presented.
Journal ArticleDOI
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
B. Feero,Partha Pratim Pande +1 more
TL;DR: 3D NoC architectures are evaluated and demonstrate their superior functionality in terms of throughput, latency, energy dissipation and wiring area overhead compared to traditional 2D implementations.
Journal ArticleDOI
3-D Topologies for Networks-on-Chip
TL;DR: An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed and the number of physical planes used to integrate the functional blocks of the network is evaluated for both the latency and power consumption of a network.
Proceedings ArticleDOI
3-D Topologies for Networks-on-Chip
TL;DR: An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed and the number of physical planes used to integrate the functional blocks of the network is evaluated for both the latency and power consumption of a network.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Networks on chips: a new SoC paradigm
Luca Benini,G. De Micheli +1 more
TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Proceedings ArticleDOI
Route packets, not wires: on-chip interconnection networks
William J. Dally,Brian Towles +1 more
TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Book
Interconnection Networks: An Engineering Approach
TL;DR: The book's engineering approach considers the issues that designers need to deal with and presents a broad set of practical solutions that address the challenges and details the basic underlying concepts of interconnection networks.