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Andrea Bandiziol
Researcher at Infineon Technologies
Publications - 15
Citations - 174
Andrea Bandiziol is an academic researcher from Infineon Technologies. The author has contributed to research in topics: Equalization (audio) & Transmitter. The author has an hindex of 5, co-authored 14 publications receiving 111 citations. Previous affiliations of Andrea Bandiziol include University of Udine.
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Proceedings ArticleDOI
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm
Andrea Bandiziol,Werner Grollitsch,Francesco Brandonisio,Matteo Bassi,Roberto Nonis,Pierpaolo Palestri +5 more
TL;DR: A novel clock-and-data-recovery (CDR) algorithm is presented to consistently deal with the combined effect of Inter-Symbol Interference (ISI) and DFE on data transitions.
Proceedings ArticleDOI
Design of a transmitter for high-speed serial interfaces in automotive micro-controller
TL;DR: This work reports about the system level design of a transmitter for the next generation of High-Speed Serial Interfaces (HSSI) to be implemented in a micro-controller for automotive Electronic Control Unit (ECU) applications, pushing the transmission speed up to 10 Gbps over a 10cm long cable.
Journal ArticleDOI
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications
TL;DR: A fully adaptive high-speed serial interface designed in 28-nm planar CMOS technology for future mobile industry processor interface (MIPI)-compliant automotive microcontrollers operating at 12 Gb/s over long-reach channels is presented.
Journal ArticleDOI
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE
TL;DR: A high-speed serial interface operating at 9.2 Gb/s for an automotive microcontroller in a 28-nm planar CMOS technology that features continuous time-linear equalization as well as decision-feedback equalization with 4 taps along with a dedicated phase-detection algorithm.
Journal ArticleDOI
A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications
Davide Menin,Thomas Bernardi,Alessio Cortiula,Martino Dazzi,Alessio De Pra,Mattia Marcon,Marco Scapol,Andrea Bandiziol,Francesco Brandonisio,Andrea Cristofoli,Werner Grollitsch,Roberto Nonis,Pierpaolo Palestri +12 more
TL;DR: This article is intended to provide a history of the project and some of the key events leading up to and during the development of the plan.