VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital very-large-scale-integration design problems. Although useful in many stages of the design cycle, fault diagnosis and logic debugging have not been addressed within a satisfiability-based framework. This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits. A number of heuristics are presented that keep the method memory and run-time efficient. An extensive suite of experiments on large circuits corrupted with different types of faults and errors confirm its robustness and practicality. They also suggest that satisfiability captures significant characteristics of the problem of diagnosis and encourage novel research in satisfiability-based diagnosis as a complementary process to design verification.

Fault diagnosis and logic debugging using Boolean satisfiability

Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors

This paper addresses the problem of combinational equivalence checking (CEC) which forms one of the key components of the current verification methodology for digital systems. A number of recently proposed BDD based approaches have met with considerable success in this area. However, the growing gap between the capability of current solvers and the complexity of verification instances necessitates the exploration of alternative, better solutions. This paper revisits the application of Satisfiability (SAT) algorithms to the combinational equivalence checking (CEC) problem. We argue that SAT is a more robust and flexible engine of Boolean reasoning for the CEC application than BDDs, which have traditionally been the method of choice. Preliminary results on a simple framework for SAT based CEC show a speedup of up to two orders of magnitude compared to state-of-the-art SAT based methods for CEC and also demonstrate that even with this simple algorithm and untuned prototype implementation it is only moderately slower and sometimes faster than a state-of-the-art BDD based mixed engine commercial CEC tool. While SAT based CEC methods need further research and tuning before they can surpass almost a decade of research in BDD based CEC, the recent progress is very promising and merits continued research.

/pdf/using-sat-for-combinational-equivalence-checking-cfqbjnswla.pdf

Using SAT for combinational equivalence checking

The paper presents a flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits. Evaluation and derivation of implications are essential in ATPG, equivalence checking, and netlist optimization. Contrary to other methods, the approach is based on a graph model of a circuit's clause description called implication graph. It combines both the flexibility of SAT-based techniques and high efficiency of structure based methods. As the proposed algorithms operate only on the implication graph, they are independent of the chosen logic. Evaluation of implications and computation of indirect implications are performed by simple and efficient graph algorithms. Experimental results for various applications relying on implication demonstrate the effectiveness of the approach.

/pdf/a-sat-based-implication-engine-for-efficient-atpg-1dg4sstida.pdf

A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists

Implication, justification, and propagation are three important Boolean problems that have to be solved during many tasks in electronic design automation (EDA) for digital circuits. As they constitute the key components of automatic test pattern generation (ATPG) most algorithms that tackle these problems originate in ATPG research. Due to their fundamental nature these ATPG-based methods have successfully been adopted by logic synthesis and formal verification where they have helped advance the fields of netlist optimization and Boolean equivalence checking. Despite their high importance and wide applicability, the data structures and algorithms suggested so far have proven to be suboptimal and inflexible in several respects. Therefore, we propose IGRAINE, a fast and flexible engine for performing implication, justification, and propagation in combinational circuits that is specifically optimized with respect to these tasks. Due to its modular design, IGRAINE is easily included into new applications that require ATPG-based methods. Our approach is based on a new implication graph (IG) model which forms the core of IGRAINE. Contrary to other IG models, the proposed IG represents all information on the implemented logic function as well as the topology of a combinational circuit in a single graph model. In order to demonstrate the performance of the presented IG-based algorithms for implication, justification, and propagation, we provide experimental results for stuck-at and path delay fault ATPG as well as Boolean equivalence checking. They show that TIP outperforms the state-of-the-art in SAT-based and structure-based ATPG. A comparison with tools for Boolean equivalence checking demonstrates the high effectiveness of our approach.

IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation

In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine As the IG model represents all information on the implemented logic function as well as the topology of a circuit, the proposed techniques inherit all advantages of both general SAT based and structure based approaches to justification, propagation, and implication These three fundamental Boolean problems are the main tasks to be performed during Automatic Test Pattern Generation (ATPG) such that the proposed algorithms are incorporated into our ATPG tool TIP which is built on top of the implication engineWorking exclusively in the IG, the complex functional operations of justification, propagation, and implication reduce to significantly simpler graph algorithms They are easily extended to exploit bit-parallel techniques As the IG is automatically generated for arbitrary logics the algorithms remain applicable independent of the required logic This allows processing of various fault models using the same engine That is, the presented IG based methods offer a complete and versatile framework for rapid development of new ATPG tools that target emerging fault models such as cross-talk, delay or bridging faults TIP currently handles stuck-at as well as various delay fault models Furthermore, the proposed methods are used within tools for Boolean equivalence checking, optimization of netlists, timing analysis or retiming (reset state computation)In order to demonstrate the performance of IG based ATPG, ie justification and propagation in the IG, we provide experimental results for stuck-at and path delay fault models They show that TIP outperforms the state-of-the-art in SAT based and structure based ATPG

/pdf/sat-based-atpg-using-fast-justification-and-propagation-in-1zaja7323d.pdf

SAT based ATPG using fast justification and propagation in the implication graph

We present a new and efficient method for path classification, i.e. for determining the set of functional unsensitizable or robust dependent paths, in combinational circuits. In a pre-processing step, the new method computes a minimal set of reconvergence regions that need to be considered for path classification. Functional sensitization is only performed for path segments contained in these regions. Thus, the complexity for path classification can be reduced from the total number of paths in the circuit to the number of paths contained in the minimal set of reconvergence regions.

/pdf/reducing-the-complexity-of-path-classification-by-19phxgv4yn.pdf

Reducing the complexity of path classification by reconvergence analysis

Automatic test pattern generation (ATPG) remains one of the most complex CAD tasks. Therefore, numerous methods were proposed to speed up ATPG by using parallelism. In this paper, we focus on parallelizing ATPG for stuck-at faults in sequential circuits by combining fault and search space parallelism. Fault parallelism is applied to so-called easy-to-detect faults. The main task of this approach is to find a best-suited partitioning of the fault list, based on dependencies between faults. For hard-to-detect faults left by fault parallelism, search space partitioning is applied, integrating depth-first and breadth-first search. Since a small test set size is mandatory for a cheap test and fault parallelism increases the number of test patterns, test set compaction is done in a post-processing phase. Results show that our approach is not only capable of achieving potentially superlinear speedups, but also improves test set quality. The parallel environment we use consists of a network of 100 workstations connected via ethernet.

Andreas Ganz

Papers

A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists

IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation

SAT based ATPG using fast justification and propagation in the implication graph

Reducing the complexity of path classification by reconvergence analysis

Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits