Showing papers in "Journal of Electronic Testing in 1997"

Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests

Abstract: We classify all path-delay faults of a combinational circuit into three categories: {\it singly-testable} (ST), {\it multiply-testable} (MT), and {\it singly-testable\ dependent} (ST-dependent). The classification uses any unaltered single stuck-at fault test generation tool. Only two runs of this tool on a model network derived from the original network are performed. As a by-product of this process, we generate single and multiple input change delay tests for all testable faults. With these tests, we expect that most defective circuits are identified. All ST faults are guaranteed detection in the case of a single fault, and some may be guaranteed detection through robust and validatable non-robust tests even in the case of multiple faults. An ST-dependent fault can affect the circuit speed only if certain ST faults are present. Thus, if all ST faults are tested, the ST-dependent faults need not be tested. MT faults cannot be guaranteed detection, but affect the speed only if delay faults simultaneously exist on a set of paths, none of which is ST. Examples and results on several ISCAS ‘89 benchmarks are presented. The method of classification through test generation using a model network is complex and can be applied to circuits of moderate size. For larger circuits, alternative methods will have to be explored in the future.

BIST Pattern Generators Using Addition and Subtraction Operations

Abstract: Configurations of adders, subtracters, or arithmetic logic units and registers, which are available in many data paths, can be utilized to generate patterns and to compact test responses. This paper analyzes the pattern sequences generated by configurations with different types of adders and subtracters. For many different seeds and constant input values, these pattern generators can produce a sequence of all possible patterns. Moreover, k-bit pattern generators that take into account the overflow or underflow bit can generate bit sequences that all have period 2^k-1. Thus, the periodicity of these pattern generators is the same as that of ak -bit linear feedback shift register with a primitive characteristic polynomial. Experimental results show that the produced pattern sequences achieve similar fault coverage as pseudorandom sequences and require about the same test length. Compared to the well-known self-test methods that insert test registers, the approach using available arithmetic units saves the additional gates that are needed to implement test registers, and it avoids performance degradation due to additional delays.

Designing “Dual Personality” IEEE 1149.1 Compliant Multi-Chip Modules

Abstract: The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture Standard can be used at many different levels in the integration hierarchy of a product. However there is one level where using the standard poses some difficulty. Multi-Chip Modules (MCM) belong to this level. This paper explores the problem and proposes a set of solutions for various classes of MCMs.

Monitoring Power Dissipation for Fault Detection

Abstract: In this paper, we suggest that the dynamic power dissipation of a circuit can be used for fault detection Even those faults which do not affect static power dissipation can be detected by monitoring dynamic power dissipation We discuss how stuck-at, stuck-open, and redundant faults may be detected by monitoring dynamic power dissipation In many cases, the Fourier spectra of the supply currents in the good and faulty circuits will also be very different Further, specific tests can be applied so as to improve fault coverage Power monitoring is verified using simulation, and also experimentally, for example circuits

Behavioral Testability Insertion for Datapath/Controller Circuits

Abstract: A method for test synthesis in the behavioral domain is described. The approach is based on the notion of adding a test behavior to the normal-mode design behavior. This test behavior describes the behavior of the design in test mode. The normal-mode design behavior and test-mode test behavior are combined and then synthesized by any general-purpose synthesis system to produce a testable design with inserted BIST structures. The test behavior is derived from the design behavior using testability analysis based on metrics that quantify the testability of signals and variables embedded within behaviors. The insertion method is combined with a behavioral test scheme that integrates a) the design controller and test controller, b) testing of the entire datapath and controller. Examples show that when the testability insertion procedure is used to modify a behavior before synthesis, the resulting synthesized physical implementation is indeed more easily tested than an implementation synthesized directly from the original behavior.

Delay Fault Coverage Enhancement Using Variable Observation Times

Abstract: Detection of system timing failures has become a very important problem whenever high speed system operation is required. It has been demonstrated that delay fault coverage loss could be significant if improper propagation paths are used. This occurs when the delay test pair of a target propagation path cannot be effectively generated by an ATPG tool, or when stuck-at test patterns are used as transition (or gate) delay test patterns. In this work, an efficient method is proposed to reduce the amount of fault coverage loss by using variable observation times. The basic idea is to offset the shorter propagation paths (really used) by tightening the observation times. Given a probability distribution of defect sizes and a set of slack differences, this method is able to locate several observation times that result in small fault coverage loss.

Exhaustive and Near-Exhaustive Memory Testing Techniques and theirBIST Implementations

Abstract: In this work we investigate the problem of detection and location of single and unlinked multiple k-coupling faults in n × 1 random-access memories (RAMs) This fault model covers all crosstalks between any k cells in n × 1 RAMs The problem of memory testing has been reduced to the problem of the generation of (n,k-1)-exhaustive backgrounds We have obtained practical test lengths, for a memory size around 1 M, for detecting up to 6-couplings by exhaustive tests and up to 9-couplings by near-exhaustive tests The best known test algorithms up to now provide for the detection of 5-couplings only in a 1 M memory, using exhaustive tests Beyond these parameters, test lengths were impractical Furthermore, our method for generation of (n,k-1)-exhaustive backgrounds yields short test lengths giving rise to considerably shorter testing times than the present most efficient tests for large n and for k greater than 3 Our test lengths are 50% shorter than other methods for the case of detecting up to 5-couplings in a 1 Mbit RAM The systematic nature of both our tests enables us to use a built-in self-test (BIST) scheme, for RAMs, with low hardware overhead For a 1Mbit memory, the BIST area overhead for the detection of 5-couplings is less than 1% for SRAM and 68% for a DRAM For the detection of 9-couplings with 99% or higher probability, the BIST area overhead is less than 02% for SRAM and 15% for DRAM

Workload Distribution in Fault Simulation

Abstract: Simulation at the gate level is computationally very expensive Parallel processing is one technique to reduce simulation time Possessing knowledge of the distribution of computational activity in simulation can aid in parallelizing it efficiently We present a new characterization of the distribution of the computational workload in fault simulation An empirical analysis shows that the workload distribution is circuit specific, and is largely independent of the vector set being simulated An inexpensive method to predict the workload distribution is also discussed

Known Good Die

Abstract: Advances in reducing size and increasing functionality of electronics have been due primarily to the shrinking geometries and increasing performance of integrated circuit technologies. Recently, development efforts aimed at reducing size and increasing functionality have focused on the first level of the electronic package. The result has been the development of multichip packaging, technologies in which bare IC chips are mounted on a single high density substrate that serves to “package” the chips, as well as interconnect them. A number of benefits accrue because of multichip packaging, namely, increased chip density, space savings, higher performance, and less weight. Therefore, these technologies are attractive for today‘s light weight, portable, high performance electronic equipment and devices. In spite of these benefits, multichip packaging has not shown the kind of explosive growth and expansion that was predicted[1]. A major inhibitor for these technologies has been the availability of fully tested and conditioned bare die, or “known good die”. This paper reviews the issues and technologies associated with test and burn-in of bare or minimally packaged IC products.

Hierarchical Delay Test Generation

Abstract: Delay testing is used to detect timing errors in a digital circuit. In this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual modules to compute robust delay tests for the module-level circuit. We present a longest path theorem at the module level of abstraction which specifies the requirements for path selection during delay testing. Based on this theorem, we propose a path selection procedure in module-level circuits and report efficient algorithms for delay test generation. MODET has been tested against a number of hierarchical circuits with impressive speedups in relation to gate-level test generation.

An Effective Multi-Chip BIST Scheme

Abstract: This paper addresses the general problem of module level test of assembled Multi-Chip Modules (MCMs) and specifically the performance test of such modules. It presents a novel solution based-on built-in self-test (BIST). This solution augments the conventional single-chip BIST approach, which is used to produce individual good dies, to an effective multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. The self-test mode not only provides effective detection of static and dynamic faults, but also identifies the failed elements, i.e., bad dies or substrate. The multi-chip self-test scheme is based on pseudo-random test generation and uses multi-signature evaluation. The hardware design of multi-chip and single-chip self-test blocks is combined under one common architecture called the Dual BIST Architecture. The paper introduces the Dual BIST Architecture and demonstrates a set of design configurations to implement it. The presented BIST solution provides a reliable static and dynamic test at the module as well as the bare die levels.

Fundamentals of MCM Testing and Design-for-Testability

Abstract: Products motivated by performance-driven and/or density-driven goals often use Multi-Chip Module (MCM) technology, even though it still faces several challenging problems that need to be resolved before it becomes a widely adopted technology. Among its most challenging problems is achieving acceptable MCM assembly yields while meeting quality requirements. This problem can be significantly reduced by adopting adequate MCM test strategies: to guarantee the quality of incoming bare (unpackaged) dies prior to module assembly; to ensure the structural integrity and performance of assembled modules; and to help isolate the defective parts and apply the repair process. This paper describes today‘s MCM test problems and presents the corresponding test and design-for-testability (DFT) strategies used for bare dies, substrates, and assembled MCMs.

Smart Substrate MCMs

Abstract: This paper presents a cost-based assessment of the effectiveness of Smart Substrate MCM Systems. A Smart Substrate MCM System is one in which the substrate contains active circuitry for carrying out testing functions. The feasibility of using this approach is investigated. The Smart Substrate strategy is compared to an alternative approach based on the assumption that system components are perfect (“Known Good Die (KGD)” approach). The obtained results identify the domain of applicability of Smart substrate MCMs and point to limitations of the KGD approach.

A Survey of Test Techniques for MCM Substrates

Abstract: This paper provides a survey of MCM substrate test techniques. Test techniques that are based on capacitance, resistance, electron beam, latent opens, time domain network analysis (TDNA) and RF resonator are discussed. In this paper, test techniques are applied to interconnect testing.

Design for Test of Crystal Oscillators: A Case Study

Abstract: A feasibility study of design-for-testability (DFT) of a voltage controlled crystal oscillator with built-in MOS switches to increase its observability and controllability is presented. The primary aim was to assess to what extent the operation of the circuit is changed when the switches are introduced. The possibility of non-destructive localization of faulty components in the provided test modes and the temperature/frequency characteristics measurements are briefly described. Finally, on the basis of the presented experimental work, a design-for-test procedure for crystal oscillator circuits is summarized. The work was performed in a development phase of a voltage controlled temperature compensated crystal oscillator.

Multiple Experiment Environments for Testing

Abstract: Concurrent simulation (CS) has been used successfully as a replacement for serial simulation. Based on storing differences from experiments, CS saves storage, speeds up simulation time and allows excellent internal observation of events. In this paper, we introduce Multiple Domain Concurrent Simulation (MDCS) which like concurrent simulation, maintains efficiency by only simulating differences. MDCS also allows experiments to interact with one another and create new experiments through the use of domains. These experiments can be traced and observed at any point, providing insight into the origin and causes of new experiments. While many experiment scenarios can be created, MDCS uses dynamic spawning and experiment compression rather than explicit enumeration to ensure that the number of experiment scenarios does not become exhaustive. MDCS does not require any pre-analysis or additions to the circuit under test. Providing this capability in digital logic simulators allows more test cases to be run in less time. MDCS gives the exact location and causes of every experiment behavior and can be used to track the signature paths of test patterns for coverage analysis. We will describe the algorithms for MDCS, discuss the rules for propagating experiments and describe the concepts of domains for making dynamic interactions possible. We will report on the effectiveness of MDCS for attacking an exhaustive simulation problem such as Multiple Stuck-at Fault simulations for digital logic. Finally, the applicability of MDCS for more general experimentation of digital logic systems will be discussed.

A Functional Decomposition Method for Redundancy Identification and Test Generation

Abstract: We present a new combinational circuit automatic test-pattern generation (ATPG) acceleration method called EST that detects equivalent search states, which are saved for later use. The search space is learned and characterized using E-frontiers, which are circuit cut-sets induced by the implication stack contents. The search space is reduced by matching the current search state against previously-encountered search states (possibly from prior faults), and this reduces the length of the search. A second contribution is a calculus of redundant faults, which enables EST to make many more mandatory assignments before search than is possible by prior algorithms, by effectively using its knowledge of prior faults proven to be redundant. This accelerates ATPG for subsequent faults. These methods accelerate the TOPS algorithm 33.3 times for the hard-to-test faults in the ISCAS ‘85 benchmarks, and the SOCRATES algorithm 5.6 times for the same hard-to-test faults, with little memory overhead.

Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

Abstract: Path delay fault model is the most suitable model for detecting distributed manufacturing defects which can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability of many practical designs is very low. In this paper we show how to resynthesize a combinational circuit in order to reduce the total number of paths in the circuit. Our results show that it is possible to obtain circuits with a significant reduction in the number of paths while not increasing area and/or delay of the longest sensitizable path in the circuit. Research on path delay testing shows that in many circuits a large portion of paths does not have a test that can guarantee detection of a delay fault. The path delay testability of a circuit would increase if the number of such paths is reduced. We show that addition of a small number of test points into the circuit can help reducing the number of such paths in the given design.

Economic Analysis of Test Process Flows for Multichip ModulesUsing Known Good Die

Abstract: The cost and quality of a multichip assembly is highly dependent upon the cost and quality of the incoming die. In the case of a bare die assembly, it is often highly desirable to use either Known Good Die (KGD) or die that have been burned-in and tested to the same level of quality and reliability as their packaged die equivalents. However, performing full bare die burn-in and test may not always be cost-effective. This paper examines the question of whether it is always necessary to use KGD to produce a cost-effective multichip module (MCM) of acceptable quality. A process-flow based cost model is used to compare the cost and quality of MCMs assembled with KGD to MCMs assembled with die that have received wafer-level test only. In addition to test effectiveness at the wafer, die, and module level, factors that are considered include die complexity (size and I/O), number of die per MCM, the cost of producing the KGD, and rework costs and effectiveness. The cost model captures inputs from wafer fabrication through MCM assembly and rework. Monte Carlo simulation is used to account for uncertainty in the input data. The resulting sensitivity analyses give final MCM cost and quality as a function of the various factors for both KGD and die that have received wafer-level test only.

Failure Analysis of VLSI by I _DDQ Testing

Abstract: A method for enhancing the popular failure techniques has been presented. The method was built on three principles: CMOS devices only draw power during switching operation; fault defects, both floating and stuck will consume power if properly conditioned; bridging fault model test programs combined with the combinational logic designs, the elevated power state should surface at some vector point prior to the location of the falling vector. A system was constructed by making use of an older vintage emission microscope. The system was configured so that direct docking to existing production hardware is possible. Using this system, five case studies were presented. The case studies proved that quiescent current signature scan analysis was successful at locating the defects within the failing units after conventional failure analysis techniques had been exhausted. Both bridging faults and floating faults were detected.

Module Level Weighted Random Patterns

Abstract: The paper describes a module level self-test architecture that uses weighted random patterns. A pseudorandom pattern generator (PRPG) is used to generate equally likely patterns that are then transformed to weighted patterns by a universal weighting generator. The module being tested is assumed to be composed of a number of chips all of which have been designed to support a scan test. The signature is collected by a multiple input signature register (MISR). Each scan latch in the module is fed by its near-optimal weight during test. In order to avoid any additional test pins, some of the existing signal pins are designated (demultiplexed) to perform a weight control function during test. This architecture can dramatically decrease the self-test time with only a small increase of hardware overhead.

MCM Test Strategy Synthesis from Chip Test and Board TestApproaches

Abstract: Chip test practices such as functional test and Bist, and their relevance to MCM testing are summarized. Drawbacks of using these techniques, for some MCMs, are presented. Board test practices such as in-circuit test and boundary-scan, are summarized; the advantages of incorporating board test techniques for certain MCMs are given. Test strategies are categorized and compared. Appropriate MCM test equipment is discussed. Examples of using chip, board, and hybrid test approaches are then given.

Delay Test Generation: A Hardware Perspective

Abstract: An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions on the kind of hardware suitable for the task, especially in built-in self-test applications where the generator must reside on chip. This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. The different options are measured based on their performance, cost, and flexibility.

Multichip Module Diagnosis by Product-Code Signatures

Abstract: A system diagnosis technique for multichip module (MCM) is presented. The proposed technique uses built-in probes for monitoring internal responses and, with a signature analysis scheme based on error correcting codes, identifies the probes where erroneous test responses have been detected. Concepts from system diagnosis is used in conjunction with signature analysis in developing the proposed MCM diagnosis technique, where the resulting patterns of the faulty probes are used in the identification of the faulty submodules (dies). The proposed technique offers a diagnostic capability in system functional test.

Improving Testability of Non-Scan Designs during BehavioralSynthesis

Abstract: We present a behavioral synthesis method aimed at generating testable datapaths. A non-scan testing strategy is targeted. Given performance and area constraints, the system is aimed at seeking among potential design alternatives the one presenting the least testability problems. The backbone of this methodology is a testability analysis method that works at different abstraction levels of the design description—from strictly behavioral domain to purely structural domain. Considering a partially mapped behavioral specification, the testability analysis identifies the testability problems of the future structure. These problems are solved along the synthesis process, for example during the register allocation/binding task as presented in this paper.

Hierarchical VLSI Fault Tracing by Successive CircuitExtraction from CAD Layout Data in the CAD-Linked EB TestSystem

Abstract: A hierarchical VLSI fault tracing method is proposed which is applicable to the case where only CAD layout data is available in the CAD-linked electron beam test system. The CAD layout data is assumed to be hierarchically structured. The method uses the expansion of a previously proposed integrated algorithm which combines a transistor-level fault tracing algorithm and a successive circuit extraction from a non-hierarchically or a flat structured CAD layout data. The method allows us to trace a fault hierarchically from the top level cell to the lowest primitive cell and from the primitive cell to the transistor-level circuit in a consistent manner independent of circuit functions even when the cell data and the transistor-level circuit data exist in a level as a mixture. An application of the method to a hierarchically structured CMOS model layout with about 600 transistors shows its validity.

An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems

Abstract: Fast and correct timing verification is a critical issue in VLSI design. Several timing verification algorithms have been proposed in the last few years. However, due to the huge computation time needed to eliminate false paths, existing algorithms have difficulty in performing timing verification for large circuits. This paper presents efficient critical path analysis algorithm based on test pattern generation with a new sensitization criterion. The algorithm does not require generation of a path list and elimination of false paths to find out the correct critical path of the circuit. The inputs which sensitize the critical path are determined as well. The efficiency and speed of our algorithm are demonstrated using the ISCAS benchmark circuits, and the critical paths are found in vastly improved times.

A Test Methodology for High Performance MCMs

Abstract: Satellite and avionics applications represent an ideal application for the tremendous performance, cost, space, and reliability benefits of MCMs. These advantages are only realized, however, if accompanied by an efficient test strategy which verifies defect-free fabrication. This paper describes a methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multi-chip silicon substrate. A test strategy, which addresses testing from the wafer level through to the populated substrate, is detailed. This strategy uses a combination of LSSD, AC LSSD-On-Chip Self Test, Deterministic Delay Fault Testing, and Design for Partitionability to ensure high test quality at a reasonable cost. The methodology is then contrasted to alternative approaches.

Simulation Techniques for the Manufacturing Test of MCMs

Abstract: Simulation techniques used in the Manufacturing Test SIMulator (MTSIM) are described. MTSIM is a Concurrent Engineering tool used to simulate the manufacturing test and repair aspects of boards and MCMs from design concept through manufacturing release. MTSIM helps designers select assembly process, specify Design For Test (DFT) features, select board test coverage, specify ASIC defect level goals, establish product feasibility, and predict manufacturing quality and cost goals. A new yield model for boards and MCMs which accounts for the clustering of solder defects is introduced and used to predict the yield at each test step. In addition, MTSIM estimates the average number of defects per board detected at each test step, and estimates costs incurred in test execution, fault isolation and repair. MTSIM models were validated with high performance assemblies at Hewlett-Packard (HP).

A Formalization of the IEEE 1149.1-1990 DiagnosticMethodology as Applied to Multichip Modules

Abstract: Much has already been written concerning the IEEE 1149.1 Boundary-Scan standard and its application to the detection of manufacturing defects [1–3]. However, when circuits such as Multichip Modules (MCMs) which are difficult and expensive to repair are involved, much more is required of a diagnostic engine than the mere detection of a defect. The cost of the dice on a module make it imperative that the diagnostic procedures implemented by a tester be exact. It is not enough to just state that “Node \langle {m}\rangle is shorted to node \langle{n}\rangle”, or that “Node \langle {p}\rangle is stuck at 1”, as is frequently the case with printed-circuit board diagnostics. MCM diagnostics must examine the data returned from the test and, as far as is possible, state not only the symptom of the fault, but also its exact cause and location. This article presents a set of formalized diagnostic rules which will, whenever possible, determine the symptom, cause, and location of a manufacturing defect.