A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists
Paul Tafertshofer,Andreas Ganz,Manfred Henftling +2 more
- pp 648-655
TLDR
A flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits based on a graph model of a circuit's clause description called implication graph which combines both the flexibility of SAT-based techniques and high efficiency of structure based methods.Abstract:
The paper presents a flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits. Evaluation and derivation of implications are essential in ATPG, equivalence checking, and netlist optimization. Contrary to other methods, the approach is based on a graph model of a circuit's clause description called implication graph. It combines both the flexibility of SAT-based techniques and high efficiency of structure based methods. As the proposed algorithms operate only on the implication graph, they are independent of the chosen logic. Evaluation of implications and computation of indirect implications are performed by simple and efficient graph algorithms. Experimental results for various applications relying on implication demonstrate the effectiveness of the approach.read more
Citations
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Fault diagnosis and logic debugging using Boolean satisfiability
TL;DR: This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits and suggests that satisfiability captures significant characteristics of the problem of diagnosis.
Proceedings ArticleDOI
Using SAT for combinational equivalence checking
TL;DR: In this article, the authors revisited the application of Satisfiability (SAT) algorithms to the combinational equivalence checking (CEC) problem and argued that SAT is a more robust and flexible engine of Boolean reasoning for the CEC application than BDDs, which have traditionally been the method of choice.
Proceedings ArticleDOI
Fault diagnosis and logic debugging using Boolean satisfiability
TL;DR: This work proposes a model-free satisfiability-based solution to Fault diagnosis and logic debugging for digital VLSI design problems and shows that satisfiability captures significant problem characteristics and it offers different trade-offs.
Proceedings ArticleDOI
Boolean satisfiability in electronic design automation
TL;DR: This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem, and highlights the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation.
Proceedings ArticleDOI
Combinational equivalence checking using satisfiability and recursive learning
Joao Marques-Silva,Thomas Glass +1 more
TL;DR: This paper shows how to improve SAT algorithms by extending and applying recursive learning techniques to the analysis of instances of SAT, which provides a new alternative and competitive approach for solving CEC.
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Proceedings Article
Socrates : A Highly Efficient Automatic Test Pattern Generation System
TL;DR: SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures.
Journal ArticleDOI
SOCRATES: a highly efficient automatic test pattern generation system
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