Andreas Sandberg

TL;DR: How the gem5 simulator has transitioned to a formal governance model to enable continued improvement and community support for the next 20 years of computer architecture research is discussed.

TL;DR: A classification of applications into four cache usage categories is introduced and how applications from different categories affect each other's performance indirectly through cache sharing is discussed and a scheme to optimize such sharing is devised.

TL;DR: A parallel sampling simulator is demonstrated that can be used to accurately estimate the IPC of standard workloads with an average error, and a novel approach is developed to estimate the error introduced by limited cache warming, through the use of optimistic and pessimistic warming simulations.

TL;DR: This paper introduces a method for efficiently investigating the performance variability due to cache contention that can estimate an application pair's performance variation 213× faster, on average, than native execution and can predict application slowdown with an average relative error.

TL;DR: The branch retention buffer is introduced, a novel mechanism that partitions only the most useful branch predictor components to isolate separate contexts and shows that, compared to the state-of-the-art, average misprediction rates are reduced by 15-20% without increasing area, leading to a 2% performance increase.